Development of Through Silicon Via (TSV) interposer for memory module flip chip package

Purpose The purpose of this study is to investigate the dynamics of capillary underfill flow (CUF) in flip-chip packaging, particularly in a multi-chip configuration. The study aims to understand how various parameters, such as chip-to-chip spacing (S12), chip thickness (tc) and others, affect the underfill flow process. By using computational fluid dynamics (CFD) simulations and experimental studies, the goal is to provide insights into understanding the dynamics of CUF in heterogeneous electronic packaging. Design/methodology/approach The paper introduces a CFD analysis and experimental study on CUF in a multi-chip configuration, aiming to understand underfill flow dynamics. A 3D geometry models of multi-chip arrangement are created using computer-aided design (CAD) software. After that, the CAD models are meshed and simulated in Ansys Fluent using incompressible and non-Newtonian fluid properties. The study maintains S12 of 2.86 and tc of 22.29 between experimental and simulation data for results validation. Next, a various of S12 values (1.14, 2.86, 5.71, 8.57, 14.29 and 20) which focus on tc of 22.29 have been investigated. Further studies have been conduct using S12 of 5.71 and tc of 8.00, 14.29 and 22.29. Findings Results show a strong correlation between simulation and experiment which validate the correctness and robustness of simulation. Further parameter’s studies using simulation for various of S12 indicated that higher S12 values lead to faster flow. This effect is due to large underfill weight from reservoir able to flow into S12 region which contributed to higher mass momentum movement. Furthermore, the effect of various of tc shows that the thicker the chip the faster the underfill to flow in S12 region. Research limitations/implications The intentional exclusion of solder bump pattern arrangements from the experiment and simulation may limit the study's ability to fully understand the impact of solder bump patterns on underfill flow. Therefore, more parameters can be investigated such as solder bump pattern, underfill weight and dispense pattern in the future using CFD. Practical implications The manuscript provides a comprehensive examination of the contributions of CFD to the advancement of knowledge regarding CUF phenomena in heterogeneous electronic packaging assemblies. Moreover, it delineates the utilization of CFD methodologies to assess the influence of chip-to-chip spacing (S12) and the thickness of the chip (tc) on the underfill flow characteristics. Originality/value This paper fulfills an identified need of computational fluid dynamics method to study capillary underfill flow dynamics in heterogenous electronic packaging.

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Bath chemistry and copper overburden as influencing factors of the TSV annealing

Saettler

Boettcher²,

Rudolph³

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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The outlined investigations represent a new systematic approach for the characterization of the copper annealing behavior in TSVs. In the center of interest are the changes in material behavior caused by bath chemistry compositions and deposition parameters during the ECD copper fill. In addition the effects on annealing behavior with or without Cu overburden are evaluated. Therefore, two bath chemistries were used for the Cu fill of one TSV test die layout. Moreover, half of the die samples underwent overburden CMP. The resulting four test die groups underwent annealing at identical conditions. The subsequent characterization featured protrusion, warpage and EBSD measurements. Results show a direct link of crystallographic defect reductions towards the tendency of developing Cu protrusion. Also deviations in warpage and crystal structure development for annealing with or without Cu overburden are presented. In conclusion the outlined investigation gains information how the Cu crystal structure develops in TSVs during annealing and links this behavior to thermo-mechanical effects like protrusion and warpage. This paper demonstrates that this behavior is dependent on the applied bath chemistry and that the presence of an overburden layer also has an influence. Deductions for an improved TSV manufacturing process can be derived from the achieved results

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Development of Through Silicon Via (TSV) interposer for memory module flip chip package

Cited by 5 publications

References 2 publications

3D Stacking of RAM–Processor Chips Using TSV

3D Stacking of RAM–Processor Chips Using TSV

Advancing packaging technology: computational fluid dynamics modeling for capillary underfill encapsulant in multi-chip heterogenous packages

Bath chemistry and copper overburden as influencing factors of the TSV annealing

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