Development of Tri‐Layered s‐Si/s‐SiGe/s‐Si Channel Heterostructure‐on‐Insulator MOSFET for Enhanced Drive Current

Abstract

Incubation of strain technology in the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) arena by developing heterostructure layers combined of Si and SiGe layers within the channel is employed widely. Development of a fully depleted novel device featuring a distinguished trilayer heterostructure channel consisting of mobility enriched double strained Si (s-Si) layers sandwiching strained SiGe (s-SiGe) in between has been the crux of this paper. The channel with s-Si/s-SiGe/s-Si significantly enhances electron mobility in comparison to conventional device of s-Si on relaxed SiGe channel, leading to improved device performance without implementing additional scaling. The tri-layered channel and the conventional device are compared and eloquent drain current enhancement of 49% attained with minimal value of threshold voltage roll-off with increased strain infusion within the channel region, which augments electron mobility in the s-Si layers. Augmented maximum transconductance for sub-50 nm channel length due to velocity overshoot enhancement of 119% in comparison to conventional device acquired lead to %25% decrease in threshold voltage by band structure lowering with the instigation of the strain technology in the short channel device attained. Hence, with higher carrier mobility and improved drive current double strained Si heterostructure on insulator (HOI) MOSFET device is designed and developed.

Physics and Modelling of Tri-Layered Strained Channel for Development of Double Gate n-channel FET

“…The calculated threshold voltage, Vth, and DIBL for DG-SHOI FET is plotted and compared with HOI MOSFET [25] and DGSOI FET [17] devices as shown in Figure 3. As evident the Vth for 22 nm DG SHOI FET is observed to be less with respect to DGSOI FET while an enormous reduction of 57.6% in DIBL is perceived, subsequently authorizing the benefit of implementing strained channel in the device.…”

“…Hence, source/drain doping concentrations are made high to reduce the channel resistance, which eventually anticipates in increasing the drive current lessening the leakage current in the proposed device. Hence, stands the motivation for scheming of the vertical channel DG-SHOI FET, which is projected to be beneficial over the planer MOSFET ensuring admirable control on the channel providing greater device performance following minimal current leakage, though highly optimistic due to incorporation of strain engineering especially for the narrow width channel region [24][25][26]. The two Si layers generates a mismatch of 4.2% in the channel with sandwiched SiGe alloy inviting strain with the band structure of the layers [30][31][32][33][34], thus, biaxial strain is realized [25,26].…”

“…The strain in the channel is applied in (010) and (001) directions as the channel is oriented in (011) direction. As the effective mass lies parallel to strain axes, strain valleys are created perpendicularly as shown in Figure 2, consequently lowers the effective mass of electrons and in turn increases the electron mobility in the system [25,31,33]. This biaxial strain in device is actuated on applying strain throughout the channel, which reduces effective mass by shifting the degeneracy levels at the conduction and valance band edges.…”

“…This result of band splitting and lowering of effective mass due to strain is in line with the atomistic calculation carried out using Density Functional Theory (DFT) [34,35] and its effect was later developed and studied for strained channel MOS transistors [36][37]. The valance and conduction band energy level splitting along the thickness of the channel alters the band structure and affect the carrier transport phenomenon as atomic lattice spacing in the region becomes loosely packed in the s-Si layers enhancing electron mobility leading to ballistic transport at nanodimensions; an oblivious occurrence with less scattering events [24,25,36]. This is supplemented with the device having nanometer scale channel length and width that endorses in increasing mobility.…”

“…Thus, velocity saturation and negligible scattering of carriers near the surface, affects in elevating mobility and drive current of the device immensely as observed by Khiangte et al [25]. Thereby, Khiangte et al [25] developed a trilayered (s-Si/s-SiGe/s-Si) channel heterostructure on insulator (HOI) planar MOSFET, where the concept of strain channel engineering was employed to modify the band structure, increasing mobility and drain current. The HOI MOSFET incubated ~49% drive current advancement for 40 nm channel length device [26].…”