Development Process for Dependable High-Performance Controllers Using Petri Nets and Fpga Technology

Wagner, Florian; Munch, Philipp; Liu, Steven; Frey, Georg

doi:10.3182/20070613-3-fr-4909.00026

Cited by 3 publications

(3 citation statements)

References 3 publications

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“…In a GSSN, two kinds of special weight control arcs, reading arc and writing arc, are introduced. In Fig.1(a), arc (P 1 ,T 1 ) is reading arc because the tokens in place S 1 3 is updated only by the weight function value of the arc (T 2 ,P 3 ), regardless of its original number. Conversion from the GSSN model to VHDL code is based on the direct mapping strategy, namely, each place is mapped to a memory element and each weight function is mapped to the combination circuit on behalf of a specific operation expression.…”

Section: Definition 2 (Firing Condition and Results Of A Transition)mentioning

confidence: 99%

“…Petri net-based digital system design method attracts the attention of many researchers, who extended the definition of Petri nets and developed related tools so as to support the entire digital system design process ranging from modeling to hardware implementation. In [1], Signal Interpreted Petri Nets (SIPN) was used to model logical controllers and a SIPN-Editor toolbox was developed that allows the design and analysis of SIPN algorithms. In order to implement algorithms on FPGA, the SIPN-Editor supports directly mapping to VHDL language.…”

Section: Introductionmentioning

confidence: 99%

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Petri Net-based Modeling and VHDL Implementation of Digital Systems

Wan¹

2016

Proceedings of the 2016 International Conference on Computer Science and Electronic Technology

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Abstract-Petri net-based digital systems modeling and hardware implementation method is well-studied. However, the existing methods are mainly applied to synchronous circuits. In this paper, a new approach is proposed for the modeling and VHDL implementation of digital systems based on an extended class of Petri nets. The generalized synchronous self-modifying net (GSSN) is defined to describe digital systems. Based on a new kind of D flip-flop, known as multi-input & multi-clock D flipflop, the specific conversion algorithm from Petri nets models to VHDL codes is presented. A design example is given to illustrate the capabilities of the proposed approach. The approach presented in the paper is suitable for both asynchronous systems and synchronous systems.

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Section: Definition 2 (Firing Condition and Results Of A Transition)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Petri Net-based Modeling and VHDL Implementation of Digital Systems

Wan¹

2016

Proceedings of the 2016 International Conference on Computer Science and Electronic Technology

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“…A lot of approaches only consider the controller behavior but not the behavior of the closed-loop, what may result in a state space explosion, when performing model-checking. The application of TNCES as a modeling language has some advantages over Petri nets, which are for example applied in [20], because discrete time can be considered and hierarchical modeling is enabled. That is essential for modeling of function calls and not least improves the clear arrangement of the models.…”

Section: Related Workmentioning

confidence: 99%

A complete framework for controller verification in manufacturing

Gerber

Preuße

Hanisch

2010

2010 IEEE 15th Conference on Emerging Technologies &Amp; Factory Automation (ETFA 2010)

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Programmable Logic Controllers (PLCs) have been established as standard devices for automation and process control since the 1990s. Although a lot of research work has been done on the field of controller modeling and verification, it is still daily practice that control software is manually developed without applying formal validation methods. On the other hand, controller modeling is often seen detached from the plant or its model, i.e. as an open loop. The results of analysis of open-loop controller behavior give very little or almost no indications of the correct behavior of the closed-loop system. The contribution therefore proposes an approach to generate formal models out of PLC code. These controller models enable formal verification of the closed loop in combination with a specification. Due to the year of publication, all solution approaches are based on the syntax definition of the IEC 61131-3, which is not fulfilled by every industrial PLC vendor. Therefore, this contribution will show a way to use the defined xml formats of the Technical Committee 6 of the PLCopen as input for the formal model generation.

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