Device‐Algorithm Co‐Optimization for an On‐Chip Trainable Capacitor‐Based Synaptic Device with IGZO TFT and Retention‐Centric Tiki‐Taka Algorithm

Abstract

Analog in‐memory computing synaptic devices are widely studied for efficient implementation of deep learning. However, synaptic devices based on resistive memory have difficulties implementing on‐chip training due to the lack of means to control the amount of resistance change and large device variations. To overcome these shortcomings, silicon complementary metal‐oxide semiconductor (Si‐CMOS) and capacitor‐based charge storage synapses are proposed, but it is difficult to obtain sufficient retention time due to Si‐CMOS leakage currents, resulting in a deterioration of training accuracy. Here, a novel 6T1C synaptic device using only n‐type indium gaIlium zinc oxide thin film transistor (IGZO TFT) with low leakage current and a capacitor is proposed, allowing not only linear and symmetric weight update but also sufficient retention time and parallel on‐chip training operations. In addition, an efficient and realistic training algorithm to compensate for any remaining device non‐idealities such as drifting references and long‐term retention loss is proposed, demonstrating the importance of device‐algorithm co‐optimization.

Analog Resistive Switching Devices for Training Deep Neural Networks with the Novel Tiki-Taka Algorithm

“…Compared to the electrochemical-RAM (ECRAM) structures, , the filamentary RRAM devices show faster programming and require voltage pulses of lower amplitude. Compared to volatile charge-based synaptic structures, the filamentary RRAM devices enable denser array implementations. Moreover, the programmed analogue conductance states show longer retention times.…”