Device and Circuit Exploration of Multi-Nanosheet Transistor for Sub-3 nm Technology Node

Abstract

A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate controllability while making the channel in the form of a sheet. The mNS-FET has superior gate controllability for the stacked channels; consequently, it can significantly reduce the short-channel effect (SCE); however, punch-through inevitably occurs in the bottom channel portion that is not surrounded by gates, resulting in a large leakage current. Moreover, as the size of the semiconductor device decreases to several nanometers, the influence of the parasitic resistance and parasitic capacitance increases. Therefore, it is essential to apply design–technology co-optimization, which analyzes not only the characteristics from the perspective of the device but also the performance from the circuit perspective. In this study, we used Technology Computer Aided Design (TCAD) simulation to analyze the characteristics of the device and directly fabricated a model that describes the current–voltage and gate capacitance characteristics of the device by using Berkeley short-channel insulated-gate field-effect transistor–common multi-gate (BSIM–CMG) parameters. Through this model, we completed the Simulation Program with Integrated Circuit Emphasis (SPICE) simulation for circuit analysis and analyzed it from the viewpoint of devices and circuits. When comparing the characteristics according to the presence or absence of bottom oxide by conducting the above research method, it was confirmed that subthreshold slope (SS) and drain-induced barrier lowering (DIBL) are improved, and power and performance in circuit characteristics are increased.

Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage

“…In our previous study on BO thickness based on the presence or absence of BO application and substrate [8], we confirmed that BO successfully reduced the leakage current. As an extension of that previous study, the current study tried to optimize PTS doping and BO at the same time; since PTS doping and BO application include capacitancevoltage (C-V) characteristics in addition to current-voltage (I-V) characteristics, the effect of reducing leakage current on various logic/memory circuits was investigated.…”

N-Type Nanosheet FETs without Ground Plane Region for Process Simplification

“…In addition, with respect to source/drain (S/D) modules, the contact depth as well as inner spacer thickness needs to be optimized [ 8 , 9 ]. It should be noted in particular that, unlike bulk FinFETs, which have already been mass produced, NS FETs have a parasitic channel underneath the first floor nanosheet [ 10 , 11 , 12 , 13 ]. Hence, even though NS FETs have multiple channels that are completely surrounded by metal gates (i.e., GAA), increased I OFF stemming from the parasitic channel is inevitable.…”

Channel Mobility Model of Nano-Node MOSFETs Incorporating Drain-and-Gate Electric Fields

“…Extension work to establish the precise device models for 3D devices such as Fin-FETs [30][31][32] or gate-all-around FETs [33,34] is still outstanding. Even though the device format is multi-nano-sheet (mNS) or multi-bridge-channel [16,[35][36][37], this concept of providing a great set of device models considering the contribution of the gate field is rather feasible. Of course, entering the 10-nm process or beyond, the current performance can be disturbed by quantum confinement effects [38][39][40].…”

“…Thus, it is necessary to give this deeper consideration, modulating all the parameters (V DS , V GS , and L mask ) at once to fully satisfy the µ eq correlated to the V DS , V GS , and channel length on drawn mask L mask . Moreover, by consolidating the adjustment of V DS and L mask correlated to the horizontal electric field and V GS influencing the vertical electric field, the drive current of MOSFETs can be more meaningful and beneficial in providing a set of accurate nano-node device models, especially beyond 28-nm node fabrication or entering 3-nm node processes [13][14][15][16]. The gate bias, which conducts the moving carriers in the channel, induces more carrier scattering, especially in surface roughness.…”