Device characteristics of the select transistor in a vertical-NAND flash memory

Abstract

In this paper, variation in parameters of select transistor of V(Vertical)-NAND flash memory is investigated for device optimization and performance evaluation. Device characteristics including threshold voltage (VTH), subthreshold swing (SS) and Off-current (IOFF) are evaluated with device parameters and those evaluations are performed with two dimensional device simulation. An equivalent structure of VNAND flash memory select transistor is suggested which includes a fully depleted silicon on insulator (SOI) MOSFET region and a bulk MOSFET region. Effects of device parameter on device performances of select transistor are investigated with physical modeling with focusing on two merged MOSFET structures. Vertical channel thickness and channel scaling affect on VTH, SS and IOFF respectively. However, corner shape in select transistor has a negligible effects on device performance. Design guidance of select transistor in V-NAND flash memory can be provided by simulation results in this work.

Improvement of Read Performance Using CMOS on Array (COA) in 3D NAND Flash

“…3D NAND Flash cell was developed to overcome many problems for 2D NAND cell. Recently, Various 3D NAND flash memories such as stacked memory array transistor (SMArT) [1]- [2] , P-BiCS [3]- [5], TCAT [6]- [7], V-NAND with SEG (Selective Epitaxial Gate) [8]- [11] and Vertical Gate [12]- [13], which consists of the thin film poly-silicon (poly-Si) channel [14]- [17] have been introduced to be the most promising nearterm solution to overcome scaling challenges in conventional planar NAND flash memories [18]- [23]. However, the side array (SA) and peripheral circuits in 3D NAND memory are like a ranch house in a crowded metropolitan downtown, where land is very precious.…”

“…Figure 2 shows the process flow to fabricate the COA structure. Firstly, NAND flash cells are fabricated using existing 3D NAND flash process flow TCAT [6]- [7], V-NAND with SEG (Selective Epitaxial Gate) [8]- [11] and Vertical Gate [12]- [13] and vTFT(vertical Thin-Film-Transistor) is used for a high-voltage transistor to control the program and erase operations with vertical channel on NAND cells structure [33]. The air gap process was applied for vTFT as shown in Figure 2 [34].…”