Device characterization and impact of CNT diameter variation on the read write stability of CNTFET 6t SRAM cell

Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

“…But in Figure 4e, despite of the larger overshoots and undershoots (�2μA) during WL's rise-time under 0.33 V supply voltage, the Logic-1 voltage-level never drops below V th in read mode (Figure 4c,d), thus all CNTFETs can act properly. In this condition, Q and QN store correct values in each write process (Figure 4c), then BL and BLB sense these values in each read process (Figure 4d), however, this 6T bitcell still has some problems in 'read mode', 'leakage current' and 'power dissipations' that has already been reported in [10,12,34,36,41,49,52,57]. As observed, the current spikes in Figure 4e cause voltagereduction (discharge) during the read process in Figure 4d.…”

“…In fact, this feature of power‐gating and also the idea of employing output inverter in read path, lead to have a stable bitcell with small powers, compared to other works (Tables 1–3). Other works often reduced delays at the cost of higher power‐consumptions [10–75].…”

“…Also, it has an acceptable leakage current and static/dynamic powers (Table 3). Note that other works were not designed for operating at threshold supply‐voltage ($${V}_{\text{DD}}$$ = $${V}_{\text{th}}$$), as well as, they just reduced their delays at the cost of higher power‐consumptions [10–75] which are not suitable for implementing in chipset of portable devices. As a result, this 11T bitcell (Figure 9) can be considered as a final optimum design that this paper tries to reach it from the beginning.…”

“…In recent decades, many efforts have been made by researchers to offer optimum designs for bitcell. They declared that thanks to the CNTs, CNTFETs have been considered as a promising alternative for Complementary Metal Oxide Semiconductors (CMOSs) in low power SRAMs [10–75], however, CNFET fabrication process still has some imperfections, including the presence of metallic carbon nanotubes ( m ‐CNTs), imperfect m ‐CNT removal processes, chirality drift, CNT doping variations, and density fluctuations, etc. [76–79].…”

“…[76–79]. Some of them exhibited comparative works to show the advantages of CNTFETs over CMOSs and FinFETs in bitcells due to extensive electrical properties of CNTs and excellent characteristics of CNTFETs [42–61]. They also reported that bitcells suffered from leakage power [10, 12, 36, 66, 67], Delay [36, 66–69], worse Read SNM [34, 49, 52, 66], negative impacts of nearthreshold supply voltage on delays and SNM [41, 68], subthreshold leakage currents [57], etc., and suggested different techniques, such as ‘decoupled R/W BLs’ [34–47, 66, 68] and ‘power‐gating’ [41, 42, 63–65], to solve those problems.…”