2017
DOI: 10.1088/2058-8585/aa8cb1
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Device engineering for high-performance, low-voltage operating organic field effect transistor on plastic substrate

Abstract: Device engineering for high-performance, low-voltage operating organic field effect transistor on plastic substrate. Flexible and Printed Electronics, 2(4), [045004].

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Cited by 10 publications
(12 citation statements)
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“…Devices operated at ultralow voltages ( V g < ‐1 V), have been reported previously but only achieved relatively low mobilities, such as 0.3 cm 2 V −1 s −1 for DDFTTF. On the other hand, high‐performance devices with charge carrier mobilities ≥ 1 cm 2 V −1 s −1 have been reported for operation voltages below 20 V . The devices that are closest in terms of mobility and threshold voltage to the transistors presented in this work operate at voltages in the range of 3–5 V …”
Section: Resultsmentioning
confidence: 67%
“…Devices operated at ultralow voltages ( V g < ‐1 V), have been reported previously but only achieved relatively low mobilities, such as 0.3 cm 2 V −1 s −1 for DDFTTF. On the other hand, high‐performance devices with charge carrier mobilities ≥ 1 cm 2 V −1 s −1 have been reported for operation voltages below 20 V . The devices that are closest in terms of mobility and threshold voltage to the transistors presented in this work operate at voltages in the range of 3–5 V …”
Section: Resultsmentioning
confidence: 67%
“…As we know for organic FETs that are free of doping and operate in the accumulation regime, V T is defined by the work function misalignment between that of the gate and the semiconductor and the trapped charge at the dielectric–semiconductor interface, and S s reflects the charge leakage at the gate interface . The density of fixed charges ( N fix ) and the density of trap states ( N trap ) at the dielectric–semiconductor interface can be further extracted from the transfer curves of devices, where the values in our case [ N fix = (3.121 ± 0.1) × 10 11 cm –2 , and N trap = (1.875 ± 0.6) × 10 10 cm –2 eV –1 ] are lower by more than one order of magnitude than the previous results, which were also based on in situ -fabricated devices from PVT-grown crystals. ,,, The S s of the ultrathin crystal devices is ∼70 mV/decade, a value that is quite small for organic FETs and even near the theoretical minimum subthreshold swing of the silicon device, revealing a high-quality gate interface …”
Section: Resultsmentioning
confidence: 99%
“…[18][19][20] Another is that the capacitance of the dielectric layer should be augmented, either by minimizing the thickness or using high-k dielectrics. 21,22 Up to now, only one work reported OLET operating below 10 V. 23 Low voltage operating devices provide ideal platform to explore the potential of charge injection/blocking layers in further enhancing the electrical and optical performances of OLETs. However, incorporation of them are lacking among those very few OLET devices operating at relatively low voltages.…”
mentioning
confidence: 99%
“…27,28 A thin layer of polystyrene was spin coated to passivate the surface. 21 Subsequently, C10-DNTT was deposited, followed by the deposition of MoO3/Ag source/drain electrodes. 29 We obtained an average saturation hole mobility of 4.3 cm 2 V -1 s -1 , with low threshold voltage and high current on-off ratio (see supporting information).…”
mentioning
confidence: 99%