Device-level and module-level three-dimensional integrated circuits created using oblique processing

Abstract

, "Device-level and module-level three-dimensional integrated circuits created using oblique processing," J. Abstract. This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D "at the device level" (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance. © The Authors. Published by SPIE under a Creative Commons Attribution 3.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.

Assessing the manufacturing tolerances and uniformity of CMOS compatible metamaterial fabrication

“…In addition to fabrication of 3D metamaterials, the MPL approach can be viewed as a generic semiconductor fabrication approach for three dimensional structures, 9 to which the inevitable question of the maximum achievable resolution using this method arises. The aim of this paper is to establish current bounds on the manufacturability of the MPL fabrication approach.…”