Device level modeling challenges for circuit design methodology in presence of variability

Juge, André; Franco, Julieta; Gouget, Gilles; Scheer, P.; Poiroux, T.

doi:10.1109/sispad.2016.7605136

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2019

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“…On the other hand, with the continuous downscaling of MOSFETs towards their ultimate physical limits, random characteristic variability is becoming an insurmountable challenge, and has been widely studied. [12][13][14][15][16][17][18][19] Characteristic variability in MOSFETs is also influenced by temperature. [20][21][22][23] Previous work has investigated the temperature dependence of variability of V th and I on .…”

Section: Introductionmentioning

confidence: 99%

Reduced variability of drain-induced barrier lowering and subthreshold slope at high temperature in bulk and silicon-on-thin-buried-oxide (SOTB) MOSFETs

Gao¹,

Mizutani²,

Takeuchi³

et al. 2019

Jpn. J. Appl. Phys.

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The temperature dependence of the variability of drain-induced barrier lowering (DIBL) and subthreshold slope (SS) is experimentally investigated in bulk and fully depleted silicon-on-thin-buried-oxide MOSFETs. Measurement results show that variability of both DIBL and SS is reduced at high temperature. The origins of these new findings are explained and confirmed by device simulations. It is found that reduced variability of DIBL at high temperature originates from randomness along the channel length direction (source–drain asymmetry), while reduced variability of SS at high temperature is mainly influenced by randomness along the channel width direction.

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