Device-level transient fault modeling

Modelling and mitigation of soft-errors in CMOS processors

“…For example, the authors in [Bar90] define the pulse length as the time between a time instance of the strike and the end of a simulation run, which is the time that a workload takes to be executed. The authors in [Rie94] and [She08] interpret a SET as a momentary pulse with a random time instance and a fixed fault length. The technique in [Rie94] deals with older CMOS technology nodes in which the length of a pulse is in the order of hundreds of nanoseconds, while [She08] determines the fault length in sub 100nm CMOS technology nodes in the order of hundreds of picoseconds.…”

“…The authors in [Rie94] and [She08] interpret a SET as a momentary pulse with a random time instance and a fixed fault length. The technique in [Rie94] deals with older CMOS technology nodes in which the length of a pulse is in the order of hundreds of nanoseconds, while [She08] determines the fault length in sub 100nm CMOS technology nodes in the order of hundreds of picoseconds. None of the above mentioned models take into account the contribution of different gates in the net list.…”

“…Single Event Effects (SEEs) have gained importance since the early nineties when several experiments repeatedly revealed that about one third of system failures are due to SEEs, rather than permanent faults [Rie94]. SEEs appear as a data corruption in the sequential or combinational logic of a digital circuit.…”

Efficient failure detection in pipelined asynchronous circuits

“…The analog behavior of transient faults by particle strikes is very close to a double exponential current injection [16]. A discrete model used to approximate the same behavior can be a glitch: a voltage pulse with the chosen duration and amplitude for the transient current strength [16].…”

“…A discrete model used to approximate the same behavior can be a glitch: a voltage pulse with the chosen duration and amplitude for the transient current strength [16]. Like in RAM cells, the glitch is usually further simplified to be single event upset (a momentary bit-flip) in synchronous logic, due to the fact that a transient change in the value of a logic circuit will not affect the computation results unless it is sampled by a memory circuit such as a flip-flop [3].…”