Device performance of sub-50 nm CMOS with ultra-thin plasma nitrided gate dielectrics

Abstract

In this paper, the physical & electrical characteristics o f ultra-thin plasma nitrided gate dielectrics are reported, aiming for sub-50 nm gate length CMOS applications. The impacts of plasma nitridation conditions on DC characteristics were investigated extensively by changing nitrogen plasma pressure, plasma immersion time, or plasma generation power. N B T l has been also investigated and the lifetime at 105C & 0.85 V operation i s estimated to be about I O years. The final current drives of 690 pA / pm for nFET and 301 pA / pm for pFET at Vdd = 0.85 V (loff = 100 nA / pm) have been achieved in sub-50 nm CMOS with optimized plasma nitrided gate dielectric with EOT <I .2 nm. introduction

Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

“…11) using analytical expressions in (8)- (12) and compare it with the procedure presented this paper. Both approaches agree with each other reasonably well (although curves at different V G do not fall on top of each other, due to the approximations involved in the obtained analytical expressions), motivating the use of these simple equations over sophisticated QM simulation in constructing the design diagram.…”

“…NBTI occurs mainly in PMOS devices under negative-voltage stress and is enhanced by inclusion of nitrogen in gate dielectrics [4]- [11]. In general, numerous studies have established the importance of the nitrogen spatial profile in dictating the boron penetration and NBTI characteristics [4], [5], [12], [13]. Such studies show that reduction of both NBTI and boron penetration requires a nitrogen profile having (comparatively) lower nitrogen near substrate-dielectric interface (for optimum NBTI) and higher nitrogen near gate-dielectric interface (for reduced boron penetration).…”

“…Thus, among the three design considerations (gate leakage, boron penetration, and NBTI) for PNO devices, several studies reported the gate leakage versus boron penetration [2]- [4] and boron penetration versus NBTI [4], [5], [12], [13] issues. However, the remaining, and perhaps equally important, optimization of gate leakage and NBTI (the topic of this paper) has never been considered.…”

“…Such studies show that reduction of both NBTI and boron penetration requires a nitrogen profile having (comparatively) lower nitrogen near substrate-dielectric interface (for optimum NBTI) and higher nitrogen near gate-dielectric interface (for reduced boron penetration). Plasma nitridation with decreasing nitrogen concentration from poly-Si/dielectric interface to substrate/dielectric interface, therefore, became an ideal choice [5], [12], [14] for oxynitride gate dielectrics. Adjustment of nitrogen profile within the dielectric of devices having plasma-nitrided oxide (PNO) ensures improved device performance in terms of boron penetration and NBTI, even down to an effective oxide thickness (EOT) of 1.1 nm [12], [13].…”

Physical models for predicting plasma nitrided Si-O-N gate dielectric properties from physical metrology

“…Extending oxynitrides to future logic generations requires meeting the International Technology Roadmap for Semiconductors (ITRS) specifications for and gate leakage [1], and plasma nitridation of gate oxides is being actively pursued [2]- [4]. Typically, short-loop capacitor or transistor lots are used to screen gate dielectric processes.…”