2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO) 2017
DOI: 10.23919/mipro.2017.7973391
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Device performance tuning of Ge gate-all-around tunneling field effect transistors by means of GeSn: Potential and challenges

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Cited by 4 publications
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“…We first notice that J P is almost identical for the three samples featuring different TDDs, witnessing a high reproducibility of the fabrication process. In contrast, J A shows a clear dependence on the TDD [25,26]. Indeed, we observe a super-linear relationship J A TDD  [27], with (V R ) values always greater than 1 (see Fig.…”
mentioning
confidence: 69%
“…We first notice that J P is almost identical for the three samples featuring different TDDs, witnessing a high reproducibility of the fabrication process. In contrast, J A shows a clear dependence on the TDD [25,26]. Indeed, we observe a super-linear relationship J A TDD  [27], with (V R ) values always greater than 1 (see Fig.…”
mentioning
confidence: 69%
“…8,9 This breakthrough enables development of devices such as high ON-current MOSFETs, [10][11][12][13][14] Schottky-barrier FETs (SBFETs), or tunnel FETs (TFETs). [15][16][17][18] However, the device performance does not depend only on the material properties of the channel, but also on the electrostatic control of the gate. Hence, the fabrication of high-k/GeSn gate stacks with a good interfacial quality is key to obtaining high performance GeSn-based devices.…”
mentioning
confidence: 99%