2008 IEEE International Test Conference 2008
DOI: 10.1109/test.2008.4700600
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DFT Architecture for Automotive Microprocessors using On-Chip Scan Compression supporting Dual Vendor ATPG

Abstract: The implementation and validation of a common DFT architecture for a new product family of PowerPC based microprocessors for various automotive applications supporting highest quality levels and low-cost test is a big challenge. When this new architecture has to satisfy the requirements of two semiconductor companies using two different CADflows based on differentATPG tools coming with incompatible on-chip scan compression solutions, the task becomes even more complex. This paper describes the result of this m… Show more

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“…As IC manufacturing technologies move to DSM (Deep Submicron) or nanometer technologies, reliability problems increase [1] [2]. Ever increasing functionality also quests for high performance.…”
Section: Introductionmentioning
confidence: 99%
“…As IC manufacturing technologies move to DSM (Deep Submicron) or nanometer technologies, reliability problems increase [1] [2]. Ever increasing functionality also quests for high performance.…”
Section: Introductionmentioning
confidence: 99%