DiAD – Distributed Acceleration for Datacenter FPGAs

Abstract

The growing demands placed upon modern compute and network resources are far exceeding the capabilities of traditional computer architectures. It is now customary for accelerators to perform the bulk of compute, and this compute is being pushed ever closer to the network. FPGA vendors have brought powerful datacenter cards to the market, combining reprogrammable FPGA fabrics with high bandwidth networking capability. However, the supporting infrastructure has yet to reach maturity, so modern and diverse workloads are not yet able to fully leverage these architectural advances.In this paper we present DiAD; a novel framework providing FPGA firmware and driver support for fully unified, distributed compute and network acceleration across a commodity Ethernet network. We present a far richer feature set and greater flexibility than other existing solutions. We show comparable networking performance from the host when compared to Xilinx's OpenNIC solution. As well as allowing for host networking through the FPGA fabric, we demonstrate reliable data transfer directly between FPGA fabrics without host intervention, and show native memory transactions sent over the network supporting pointer-chasing workloads. We achieve line rate for dataflow type communication and approach line rate for larger native memory transfers (87G). This is the author's version of the work. It is made available only for personal use. Not for redistribution. The definitive Version of Record is to be published in the proceedings of the 33rd International Conference on Field-Programmable Logic and Applciations (FPL'23), Sept 4-8, 2023.1 DiAD focuses on AMD/Xilinx devices as the use of the proprietary QDMA IP is central to the design.