Diagnosis of full open defects in interconnect lines with fan-out

Rodríguez-Montañés, R.; Arumí, D.; Figueras, Joan; Einchenberger, S.; Hora, C.; Kruseman, B.

doi:10.1109/etsym.2010.5512752

Cited by 8 publications

(3 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Also while previous papers [3] [5] [6] considers only pairwise bridging faults, the fault model assumed in this paper includes bridging faults of all cardinalities. Also, a faulty net has only a single fault therefore for such a net having multiple branches, a fault (stuck-at and/or bridging) on any one of its branches will affect all branches of this net (non-unidirectional property in propagation) [18]; this feature is applicable to FPGAs due to the non buffered nature of these signals [17]. In addition, LUTs, flip-flops and latches are considered to be pretested.…”

Section: Review and Preliminariesmentioning

confidence: 99%

A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects

Almurib

Kumar

Lombardi

2011

2011 Asian Test Symposium

View full text Add to dashboard Cite

This paper presents a new method for applicationdependent testing of SRAM-based FPGA interconnects at run time. This method utilizes new features related to the function for the programming of the LUTs, the utilization (by logic activation/deactivation) of the nets in a interconnect configuration as well as the primary (unused) IOs of the FPGAs. A new LUT programming function is introduced; the proposed method retains the original interconnect configuration and modifies the function of the LUTs using the so-called 1-Bit Sum Function (1-BSF); the 1-BSF detects all possible stuck-at and bridging faults (of all cardinalities) by utilizing the all zeros' vector and a walking-1 test set. As validated by simulation for benchmark circuits (implemented on the Xilinx Virtex4), the proposed method results in a single test configuration with 100% coverage under the assumed fault model.

show abstract

Section: Review and Preliminariesmentioning

confidence: 99%

A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects

Almurib

Kumar

Lombardi

2011

2011 Asian Test Symposium

View full text Add to dashboard Cite

show abstract

“…Although previous papers [2,[6][7][8] consider only pairwise bridging faults, the fault model assumed in this paper includes bridging faults of all cardinalities. Also, a faulty net has only a single fault, therefore for such a net having multiple branches, a fault (stuck-at and/or bridging) on any one of its branches will affect all branches of this net (non-unidirectional property in propagation) [25]; this feature is applicable to FPGAs because of the non-buffered nature of these signals [26]. In addition, LUTs, FFs and latches are considered to be pretested (as also assumed in previous papers [2,7]).…”

Section: Review and Preliminariesmentioning

confidence: 99%

Single‐configuration fault detection in application‐dependent testing of field programmable gate array interconnects

Kumar

Almurib

Lombardi

2013

IET Computers & Digital Techniques

View full text Add to dashboard Cite

This study presents a new method for application testing of field programmable gate array (FPGA) interconnects at run time. This method utilises new features related to the function for the programming of the look up tables (LUTs), the utilisation (by logic activation/deactivation) of the nets in a interconnect configuration as well as the primary (unused) input/outputs (IOs) of the FPGAs. A new LUT programming function is introduced; the proposed method retains the original interconnect configuration and modifies the function of the LUTs using the so-called 1-bit sum function (1-BSF); the 1-BSF detects all possible stuck-at and bridging faults (of all cardinalities) by utilising the all zeros' vector and a walking-1 test set. As validated by simulation for benchmark circuits (implemented on the Xilinx Virtex4 and Virtex5), the proposed method (with a polynomial time complexity) results in a single test configuration with 100% coverage. These results also show that the proposed method requires a larger number of test vectors and an availability of unused IOs.

show abstract

“…The work in [27] does not require the knowledge of neighboring coupling capacitances at the expense of requiring a certain number of failing patterns, although this is not always the case. Finally, a technique considering the impact of transistor parasitic capacitances and the Byzantine problem is presented in [28] and [29].…”

Section: Introductionmentioning

confidence: 99%

Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents

Arumí

Rodríguez-Montañés

Figueras

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Accurate diagnosis of open defects is key to identifying process problems and achieving fast yield improvement. Current diagnosis methodologies for interconnect full open defects have demonstrated their efficiency, assuming that the defective line voltage is mainly determined by neighboring lines and downstream transistor parasitic capacitances. However, the continuous reduction of oxide thickness with every technology node increases gate leakage current significantly, even for highk dielectrics. In this context, in nanometer CMOS technologies, the defective line cannot be assumed to be electrically isolated because of the impact of gate leakage currents, which may invalidate diagnosis results provided by present methodologies. In this paper, a new methodology is proposed to diagnose interconnect full open defects under the influence of gate leakage currents in CMOS technologies.To the authors' knowledge, such influence has not been previously considered by any of the existing methodologies. Simulation and experimental results demonstrate the proposal efficiency.

show abstract

Diagnosis of full open defects in interconnect lines with fan-out

Cited by 8 publications

References 18 publications

A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects

A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects

Single‐configuration fault detection in application‐dependent testing of field programmable gate array interconnects

Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents

Contact Info

Product

Resources

About