Diagnosis of segment delay defects with current sensing

Aljubouri, Wisam; Somashekar, Ahish Mysore; Haniotakis, T.; Tragoudas, Spyros

doi:10.1109/dft.2014.6962101

Cited by 3 publications

(12 citation statements)

References 16 publications

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“…These results indicate the promise of the method. The proposed method uses fundamental concepts for measuring accurately the delay of an embedded path using current sensors that were introduced recently in [11]. However, there is a significant differences between the proposed method and [11].…”

Section: Introductionmentioning

confidence: 91%

“…However, there is a significant differences between the proposed method and [11]. The method in [11] uses multiple current sensors which must be inserted on certain positions of the power lines. This requires modifications in the layout and hardware overhead is introduced.…”

Section: Introductionmentioning

confidence: 97%

“…The proposed method uses fundamental concepts for measuring accurately the delay of an embedded path using current sensors that were introduced recently in [11]. However, there is a significant differences between the proposed method and [11]. The method in [11] uses multiple current sensors which must be inserted on certain positions of the power lines.…”

Section: Introductionmentioning

confidence: 97%

“…Section 2 gives preliminaries overviews the current sensing method in [11] and outlines the difference between [11] and the proposed technique. The proposed method is presented in Section 3.…”

Section: Introductionmentioning

confidence: 99%

“…In particular, [11] measures the delay of a embedded path P using a single test vector whereas the proposed formulation requires two test vectors which are generated to measure the delay of two other paths that are correlated to P .…”

Section: Introductionmentioning

confidence: 99%

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Identification of delay defects on embedded paths using one current sensor

Aljubouri

Tragoudas

Haniotakis

2016

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

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This paper is focused on developing an ATPG-based method that is orthogonal to existing post-silicon debug methods for delay defects. Given an embedded path that contains a small number of gates, the proposed ATPG generates two test vectors so that a current sensor can measure its delay with high accuracy. Unless the cumulative defect along the path is very small, the proposed method will either determine that all locations on it are fault-free or some are defective. This will benefit postsilicon debug methods and, ultimately, failure analysis. No modifications are required in the circuit layout and the routing of the power lines. Experimental results on some of the largest ISCAS85, ISCAS89 and ITC99 benchmarks show that the proposed ATPG tool is capable of generating test vectors which measure the delay of embedded paths that cover on average approximately one fourth of the gates. These results indicate the promise of the method.

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Section: Introductionmentioning

confidence: 91%

Section: Introductionmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Identification of delay defects on embedded paths using one current sensor

Aljubouri

Tragoudas

Haniotakis

2016

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

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Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements

Somashekar

Tragoudas

2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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An approach capable of identifying the locations of distributed small delay defects, arising due to manufacturing aberrations, is proposed. It is shown that the proposed formulation can be transformed into a Boolean Satisfiability form to be solved by any SAT solver. The approach is capable of providing a small number of alternative sets of potential defective segments, and one of the solutions is the actual defect configuration. This is shown to be a very important property towards the effective identification of the defective segments. Experimental analysis on ISCAS and ITC benchmark suites show that the proposed approach is highly scalable and identifies the location of multiple delay defects.

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Detection of Low Power Trojans in Standard Cell Designs using Built-in Current Sensors

Shanyour

Tragoudas

2018

2018 IEEE International Test Conference (ITC)

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Diagnosis of segment delay defects with current sensing

Cited by 3 publications

References 16 publications

Identification of delay defects on embedded paths using one current sensor

Identification of delay defects on embedded paths using one current sensor

Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements

Detection of Low Power Trojans in Standard Cell Designs using Built-in Current Sensors

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