Diagnostic testing of embedded memories based on output tracing

Niggemeyer, D.; Redeker, M.; Rudnick, E.M.

doi:10.1109/mtdt.2000.868624

Cited by 17 publications

(9 citation statements)

References 14 publications

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“…For any address order and memory background, the number of detectable memory faults including the NPSF will be the same and can be calculated according to the memory test detection ability (Niggemeyer et al, 2000;Niggemeyer et al, 1998). In the case of multiple-run memory test execution, the consecutive memory address order and background are very important for the achievement of a high fault coverage (Yarmolik and Yarmolik, 2006b).…”

Section: Introductionmentioning

confidence: 99%

Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests

Yarmolik¹

2008

International Journal of Applied Mathematics and Computer Science

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It is widely known that pattern sensitive faults are the most difficult faults to detect during the RAM testing process. One of the techniques which can be used for effective detection of this kind of faults is the multi-background test technique. According to this technique, multiple-run memory test execution is done. In this case, to achieve a high fault coverage, the structure of the consecutive memory backgrounds and the address sequence are very important. This paper defines requirements which have to be taken into account in the background and address sequence selection process. A set of backgrounds which satisfied those requirements guarantee us to achieve a very high fault coverage for multi-background memory testing.

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Section: Introductionmentioning

confidence: 99%

Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests

Yarmolik¹

2008

International Journal of Applied Mathematics and Computer Science

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“…Generally, diagnosis approaches for memories are based on a signature analysis [2] and the Diagnosability Ratio (DR) is a parameter used to measure the quality of a diagnostic algorithm. Diagnostic methods generally resort to a fault dictionary and try to achieve the highest diagnosability ratio for a given test algorithm [3,4,5,6].…”

Section: Introductionmentioning

confidence: 99%

A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs

Ney

Bosio

Dilillo

et al. 2008

2008 IEEE International Test Conference

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The usual techniques for memory diagnosis are mainly based on signature analysis. They consist in creating a fault dictionary that is used to determine the correspondence between the signature and the fault models affecting the memory. The effectiveness of such diagnosis methods is therefore strictly related to the fault dictionary accuracy. To the best of our knowledge, most of existing signature-based diagnosis approaches targets static faults only. In this paper, we present a new diagnosis approach that represents an alternative to signature-based approaches. This new diagnosis technique, named history-based diagnosis, makes use of the effect-cause paradigm already developed for logic design diagnosis. It consists in creating a database containing the history of operations (read and write) performed on a faulty memory core-cell. This information is crucial to track the root cause of the observed faulty behavior and it can be used to generate the set of possible Fault Primitives representing the set of suspected fault models. This new diagnosis method is able to identify static as well as dynamic faults. Although applied to SRAMs in this paper, it can be effective also for other memory types such as DRAMs. Experimental results are provided to prove the efficiency of the proposed methodology in generating a list of suspected faults as well as the location of the faulty components in the memory.

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“…It is defined as the ratio of the number of distinguishable fault types among the number of total detectable fault types. Diagnosis methods generally use a fault dictionary and try to achieve the highest diagnosability ratio for a given test algorithm [9,10,11,12]. However, these solutions are most of the time unable to distinguish between all faults (or all fault models) and hence do not allow to determine which block of the memory is defective.…”

Section: Introductionmentioning

confidence: 99%

An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing

Ney

Girard

Pravossoudovitch

et al. 2008

26th IEEE VLSI Test Symposium (Vts 2008)

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Diagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, and its effectiveness allows a fast yield ramp up. Most of existing diagnosis methods uses a fault dictionary to provide detailed information on fault localization. However, these solutions are most of the time unable to distinguish between all faults, and more importantly often fail to identify the actual faulty block of the memory. Identifying which block of a memory (corecell array, write drivers, address decoders, pre-charge circuits, etc …) is defective allows to saving considerable amount of time during the ramp up phase.In this paper, we propose a very low cost Design-for-Diagnosis (DfD) solution for identifying faulty write drivers. It consists in verifying logic and analog conditions that guarantee the fault-free behavior of the write driver. The proposed solution allows a fast diagnosis (only three consecutive write operations are needed to fully diagnose the write driver) and induces a low area overhead (about 0.5% for a 512x512 SRAM). Beside diagnosis, an additional interest of such a solution is its usefulness during a post-silicon characterization process, where it can be used to extract the main features of the write drivers (logic and analog levels on bit lines).

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Diagnostic testing of embedded memories based on output tracing

Cited by 17 publications

References 14 publications

Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests

Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests

A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs

An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing

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