DICE-based muller C-elements for soft error tolerant asynchronous ICs

Danilov, Igor A.; Gorbunov, Maxim S.; Shnaider, Alexandra I.; Balbekov, Anton O.; Rogatkin, Yuri B.; Bobkov, Sergey G.

doi:10.1109/radecs.2016.8093145

Cited by 10 publications

(2 citation statements)

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“…The sequential elements can be latch or FF based, latch-based typically being more flexible and lower power [17]. Making these designs radiation hardened has often focused on the unique aspects of the asynchronous nature -the asynchronous control logic [33], [34]. One of the simplest approach is dual-modular redundancy with guardgates [35].…”

Section: Related Workmentioning

confidence: 99%

SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol

Aketi

Gupta

Cheng

et al. 2020

IEEE Trans. Circuits Syst. I

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The risk of soft errors due to radiation continues to be a significant challenge for engineers trying to build systems that can handle harsh environments. Building systems that are Radiation Hardened by Design (RHBD) is the preferred approach, but existing techniques are expensive in terms of performance, power, and/or area. This paper introduces a novel soft-error resilient asynchronous bundled-data design template, SERAD, which uses a combination of temporal and spatial redundancy to mitigate Single Event Transients (SETs) and upsets (SEUs). SERAD uses Error Detecting Logic (EDL) to detect SETs at the inputs of sequential elements and correct them via re-sampling. Because SERAD only pays the delay penalty in the presence of an SET, which rarely occurs, its average performance is comparable to the baseline synchronous design. We tested the SERAD design using a combination of Spice and Verilog simulations and evaluated its impact on area, frequency, and power on an open-core MIPS-like processor using a NCSU 45nm cell library. Our post-synthesis results show that the SERAD design consumes less than half of the area of the Triple Modular Redundancy (TMR), exhibits significantly less performance degradation than Glitch Filtering (GF), and consumes no more total power than the baseline unhardened design.

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Section: Related Workmentioning

confidence: 99%

SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol

Aketi

Gupta

Cheng

et al. 2020

IEEE Trans. Circuits Syst. I

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“…Various radiation-hard techniques have been developed and verified, e.g. hardware Triple Modular Redundancy (TMR) [3], Dual Interlocked Storage Cell (DICE) [4], Junction Isolated Common Gate (JICG) [5], etc. These radiation-hard techniques show significant improvement of fault tolerance to radiation, i.e.…”

Section: Introductionmentioning

confidence: 99%

Optical Fault Injection Attacks against Radiation-Hard Shift Registers

Petryk

Dyka

Sorge

et al. 2021

2021 24th Euromicro Conference on Digital System Design (DSD)

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If devices are physically accessible optical fault injection attacks pose a great threat since the data processed as well as the operation flow can be manipulated. Successful physical attacks may lead not only to leakage of secret information such as cryptographic private keys, but can also cause economic damage especially if as a result of such a manipulation a critical infrastructure is successfully attacked. Laser based attacks exploit the sensitivity of CMOS technologies to electromagnetic radiation in the visible or the infrared spectrum. It can be expected that radiation-hard designs, specially crafted for space applications, are more robust not only against high-energy particles and short electromagnetic waves but also against optical fault injection attacks. In this work we investigated the sensitivity of radiation-hard JICG shift registers to optical fault injection attacks. In our experiments, we were able to trigger bit-set and bit-reset repeatedly changing the data stored in single JICG flip-flops despite their high-radiation fault tolerance.

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