DiCo-CMP: Efficient cache coherency in tiled CMP architectures

Abstract

Future CMP designs that will integrate tens of processor cores on-chip will be constrained by area and power. Area constraints make impractical the use of a bus or a crossbar as the on-chip interconnection network, and tiled CMPs organized around a direct interconnection network will probably be the architecture of choice. Power constraints make impractical to rely on broadcasts (as Token-CMP does) or any other brute-force method for keeping cache coherence, and directory-based cache coherence protocols are currently being employed. Unfortunately, directory protocols introduce indirection to access directory information, which negatively impacts performance. In this work, we present DiCo-CMP, a novel cache coherence protocol especially suited to future tiled CMP architectures. In DiCo-CMP the role of storing up-to-date sharing information and ensuring totally ordered accesses for every memory block is assigned to the cache that must provide the block on a miss. Therefore, DiCo-CMP reduces the miss latency compared to a directory protocol by sending coherence messages directly from the requesting caches to those that must observe them (as it would be done in brute-force protocols), and reduces the network traffic compared to Token-CMP (and consequently, power consumption in the interconnection network) by sending just one request message for each miss. Using an extended version of GEMS simulator we show that DiCo-CMP achieves improvements in execution time of up to 8% on average over a directory protocol, and reductions in terms of network traffic of up to 42% on average compared to Token-CMP.

Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors

“…This prediction based on previous recent history is similar to the one proposed by Martin et al [52]. Other works also benefit from this observation with different aims [7,65,66].…”

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

“…However, these traditional cache coherence protocols introduce indirection in the critical path of cache misses [13]. To solve the problem of indirection, Token-CMP [14] and DiCo-CMP [15] protocols have been proposed. These indirection-aware protocols avoid the access to the home node allowing latency of cache misses to be reduced.…”

Cuckoo directory: A scalable directory for many-core systems

“…Among these are: Tagless directories [43] from Zebchuk et al, demonstrated to be highly area-efficient but not energyscalable; SCI [20] from James et al, using sharer pointers in the private caches rather than a directory structure; token coherence [27] from Martin and Hill, also avoiding a coherence directory; software-controlled address indirection by Fensch and Cintra [14] and Hardavellas et al [19] handle coherence in software on shared cache substrates; and DiCo [32] from Ros et al, eliminating directories in favor of storing coherence information within the cache tags.…”