Die Edge Crack Propagation Modeling for Risk Assessment of Advanced Technology Nodes

Xu, Tingge; Wu, Zhuo-Jie; Zhang, Haojun; Graas, Carole; Justison, Patrick

doi:10.1109/ectc.2018.00340

Cited by 10 publications

(2 citation statements)

References 16 publications

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“…19,23 The crackstops are added to the node's process design kit and processed with the standard processing available to its respective node. Usually, the die corners are more vulnerable 24 to delamination via crack propagation; thus, a crack-stop may be made more robust at the die corners, as shown by Rabie et al, 22 in both layout views and confocal scanning acoustic microscopy images. As seen in the listed references mentioned, the crack-stops or seal rings are made primarily in the back-end-of-line (BEOL) with BEOL processing.…”

Section: Introductionmentioning

confidence: 99%

Minimizing die fracture in 3DIC die integration

Bravo,

Morey-Chaisemartin,

Beisser

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

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Background: The demand for high-performance semiconductor products has led to reduced wafer feature size, lowered package size, and an ever-thinner die for advanced three-dimensional (3D) packaging. Dies down to a thickness of 5 μm have been demonstrated. One significant barrier is the fragility of the thin dies, their overall thin form factor, and their impact on yield, reliability, and costs.Aim: We explore the current state of the art in the current crack stop and outline the shortcomings moving forward for stacked 3D integrated circuits (3DIC).Approach: Using a theoretical understanding of fracture mechanics and the new biomimetic concept adapted from nature, we show the implementation of the new crack stop insertions in the die frame for a next-generation 3DIC product. Results:The proposed crack stop can be easily inserted in the die frame with electronic design automation (EDA) tools using a Python interpreter and has the capability to arrest a crack near its initiation point. Conclusions:We show the feasibility of the implementation through EDA tools and outline the next step.

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Section: Introductionmentioning

confidence: 99%

Minimizing die fracture in 3DIC die integration

Bravo,

Morey-Chaisemartin,

Beisser

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

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“…The reliability of a WLCSP needs to be thoroughly assessed and understood before implementing this assembly technology for production. It is well known that the chippackage interaction (CPI) in flip chip can result in reliability fails such as white bump, die corner crack and delamination, and solder fatigue [4][5][6][7]. In WLCSP, chip is directly attached to PCB which has drastically dissimilar material properties compared to chip.…”

Section: Introductionmentioning

confidence: 99%

Understanding and Improving Reliability for Wafer Level Chip Scale Package: A Study Based on 45nm RFSOI Technology for 5G Applications

Zhang

Malinowski

2020

IEEE J. Electron Devices Soc.

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Wafer level chip scale package (WLCSP) is true chip scale package with low cost by eliminating package substrate. The direct chip-to-board attach through solder joints provides low interconnect inductance and resistance, as well as improved thermal performance. These properties make WLCSP a packaging format well suited for 5G radio frequency (RF) applications where minimized package size and parasitics as well as thermal performance are critical. Due to the dissimilar properties between chip and board, the reliability of WLCSP can be challenging. This paper reports a reliability study of WLCSP using 45nm RFSOI technology for 5G RF applications. Dedicated test chips and boards were designed and used for board level reliability tests. The test vehicles passed bHAST and drop test, whereas it is found that temperature cycling on board (TCoB) is challenging for solder joint reliability in some cases. Thorough tests were carried out based on Kelvin test on specially designed individual bump and bump pair structures and developed fail criterion. Finite element modeling was adopted to simulate the reliability performance in different configurations. The impact on reliability performance from bump depopulation, die thickness, bump size, UBM to board pad alignment, and board wiring trace were thoroughly investigated. Based on comprehensive testing and deep understanding of the failure mechanisms, design optimizations for chip, board and interconnect were implemented. WLCSP reliability was significantly improved.

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