Dielectric Breakdown of SiO2 Grown on Rough Si Surfaces

Gambino, J.; Nguyen, Thanh Thi; Cunningham, B.; Shepard, J.

doi:10.1007/978-1-4899-0774-5_49

Cited by 8 publications

(5 citation statements)

References 12 publications

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“…Plasma exposure is known to produce substrate damage up to a depth of several nanometers below etched Si surfaces, [21][22][23][24][25][26][27][28][29] and there is ample evidence that some of the damage remains at or near the Si/SiO 2 interface after thermal oxidation. For example, RIE damage is reported to reduce the gate-oxide-integrity (GOI) of MOS devices formed on plasma-exposed Si, unless more than 20 nm of the etched Si surface is removed by growing a sacrificial oxide prior to the gate oxide formation.…”

Section: Resultsmentioning

confidence: 99%

“…28 Likewise, TEM observations reveal that RIE induced surface roughness propagates to the Si/SiO 2 interface during thermal oxidation. 29 Therefore, capacitors produced in the manner described above should have two distinct levels of Si/SiO 2 interfacial damage either at or certainly less than 20 nm below the Si surface: an intrinsic level at unexposed regions and an RIE-induced level at exposed regions. One of the most frequently observed electrical effects of plasma exposure is shifting of the Si surface potential which lowers Schottky barrier heights on n-type substrates and increases them on p-type substrates.…”

Section: Resultsmentioning

confidence: 99%

“…It has been proposed [11][12][13] that such contrast behavior is caused by local thinning of the oxide, based on the notion that the low bias signal is dominated by the electron beam generation of carriers in the oxide layer, for which a thinner oxide region would have a smaller volume of interaction with the incident electron beam. Whereas, at high biases [11][12][13]29,30 thin sites produce an enhanced current (dark) contrast because tunneling currents increase inversely with the thickness. While this statement is certainly true for dark-currents, it is not entirely obvious whether the combination of an enhanced dark-current density and a reduced volume of oxide/electron-beam interaction leads to dark contrast at thinning sites.…”

Section: Resultsmentioning

confidence: 99%

See 2 more Smart Citations

Bias Dependent Contrast Mechanisms in EBIC Images of MOS Capacitors

Kirk

Radzimski²,

Romanowski

et al. 1999

J. Electrochem. Soc.

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Defects and inhomogeneities in the electrical properties of metal oxide silicon capacitors are analyzed by scanning electron microscopy, using the electron beam induced current technique (MOS/EBIC). All capacitors were analyzed in their as‐fabricated or prebreakdown condition. The collected signals and image contrast are found to be highly dependent on the gate‐to‐substrate bias applied during MOS/EBIC examination, and this bias‐dependence is shown to be correlated with the nature and physical location of the defect. Specific MOS defects were selected for this study according to their position in the substrate, in the oxide, or at the normalSi/SiO2 interface. Substrate defects examined were misfit dislocations in epitaxial Si(Ge) on Si. Interfacial inhomogeneities included thermally oxidized, reactive ion etched (RIE) Si surfaces, and SiO2 precipitates or “D‐defects” which extend to meet the Si surface. Oxide layer inhomogeneities were also detectable which exhibited a strong contrast dependence on the oxide electric field strength. © 1999 The Electrochemical Society. All rights reserved.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Bias Dependent Contrast Mechanisms in EBIC Images of MOS Capacitors

Kirk

Radzimski²,

Romanowski

et al. 1999

J. Electrochem. Soc.

View full text Add to dashboard Cite

show abstract

“…It is likely that the last step in the D clean, consisting of wafer treatment in an HCI:Ar afterglow, may cause localized silicon pitting. The resulting surface roughness, which is known to adversely affect dielectric strength of the gate oxide (8,9), may be responsible for the inferior breakdown statistics observed in this case.…”

Section: Table II Electrical Parameters Of Mos Devices For Three Diff...mentioning

confidence: 93%

Electrical Evaluation of Wet and Dry Cleaning Procedures for Silicon Device Fabrication

Rużyłło

Hoff

Frystak

et al. 1989

J. Electrochem. Soc.

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Three different cleaning procedures of silicon wafers are investigated: (i) standard wet clean, (ii) combination of UV/ oxygen and wet cleans, and (iii) entirely dry clean consisting of UV/oxygen, and thermally enhanced remote microwave ABSTRACT Using point contact Josephson junctions fabricated by Y-Ba-Cu-O high-Tc superconductors, Shapiro steps (ac Josephson effect) were observed. It was found that condensed pair electrons exist in high-Tc ceramics. AC Josephson effect was observed at 77 K when the device was fabricated by the samples made by the proposed liquid quenching method.Recently discovered ceramics (Y-Ba-Cu-O system) with ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 138.38.0.53 Downloaded on 2015-06-17 to IP

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“…8 Previous studies [9][10][11] indicate that offaxis Si͑100͒ substrate ͑i͒ has higher oxide defect density due to increased surface roughness which enhances nonuniform oxidation and creation of weak thin spots in the oxide and ͑ii͒ exhibits larger interface charges and a larger thresholdvoltage shift than that of on-axis Si͑100͒ starting material. It is known that oxidation rate for different silicon crystal planes has the following trend: Si͑111͒ Ͼ Si͑110͒ Ͼ Si͑100͒.…”

Section: Oxide Growth Ratementioning

confidence: 99%

Influence of starting material on analog technology fabrication yield and device component performance

Mahalingam

Knerr

et al. 2007

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Development of high-performance fully depleted silicon-on-insulator based extended-gate field-effect transistor using the parasitic bipolar junction transistor effect Appl. Phys. Lett. 101, 133703 (2012); 10.1063/1.4757000Integration of strained and relaxed silicon thin films on silicon wafers via engineered oxide heterostructures: Experiment and theory J. Appl. Phys. 108, 073526 (2010); 10.1063/1.3486217 Ion dose, energy, and species dependencies of strain relaxation of SiGe buffer layers fabricated by ion implantation techniqueChoice of substrate used for analog complementary metal-oxide-semiconductor ͑CMOS͒ technologies impacts device performance and fabrication yields significantly. This study examines the impact of low-angle ͑Ͻ5°͒ off-axis Si͑100͒ substrate rotated around ͗110͘ axis and 0°Si͑100͒ on-axis starting material on inline process control, parametric device performance, and ultimately fabrication yields. The interaction of thermal processes and silicon epitaxial growth process variation on inline photoalignment and its influence on device design and performance is discussed for both types of substrates. The device components include 3 and 5 V analog CMOS, lateral p-n-p bipolar transistor, junction field effect transistors, and drain extended transistors, DENMOS and DEPMOS, where the drain extensions are formed using well implants. The necessity to reintegrate silicon epitaxial growth, well photolithography and implants, Vt implants, and gate oxide process loop to accommodate substrate crystal orientation changes will be presented. A novel front-end-of-the-line integration scheme to improve interwafer and intrawafer electrical distributions with excellent transistor matching and 1 / f noise performance for aforementioned device components will also be discussed in this context.

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Dielectric Breakdown of SiO2 Grown on Rough Si Surfaces

Cited by 8 publications

References 12 publications

Bias Dependent Contrast Mechanisms in EBIC Images of MOS Capacitors

Bias Dependent Contrast Mechanisms in EBIC Images of MOS Capacitors

Electrical Evaluation of Wet and Dry Cleaning Procedures for Silicon Device Fabrication

Influence of starting material on analog technology fabrication yield and device component performance

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