Dielectric Material and Thermal Optimization in Sidewall Spacer Design for Junctionless Nanosheet FETs at Sub- 5 nm Technology Node: An Insight into Device and Circuit Performance

Abstract

This study focuses on the design and analysis of Junctionless (JL) NSFETs, with an emphasis on the influence of spacer materials and temperature variations. A different number of materials such as Air, SiO2, Si3N4, HfO2, and TiO2 are examined for sidewall spacer compatibility in the JL-NSFET. The same materials are used for dual material spacers with combinations of: Air+HfO2, Air+TiO2, SiO2+HfO2, and SiO2+TiO2. The investigations revealed that the usage of TiO2 material gives better digital and analog performance with reduced leakage currents and subthreshold swing (SS), higher on/off ratio, voltage gain of ~79.7 dB. Exploring the dual-k spacers produced better analog performance, gate control and reduced leakages for SiO2+TiO2 owing to the usage of higher dielectric material towards the gate. Further, the reduction of temperature from 400 K to 250 K for all the single-k and dual-k spacer materials revealed that the designed JL-NSFET is a suitable candidate at lower temperatures to improve the digital and analog performance whereas not recommended for RF performance improvement. Moreover, the SiO2+HfO2 spacer-based CMOS inverter is noticed to have better gain (~15V/V), noise margin, and lower delays (~5.1 ps) when compared to TiO2 spacer-based complementary metal oxide semiconductor inverter making it suitable for digital IC applications.