Differential bidirectional transceiver for on-chip long wires

Huang, Hong-Yi; Pu, Ruei-Iun

doi:10.1016/j.mejo.2011.08.001

Cited by 15 publications

(11 citation statements)

References 15 publications

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“…Following the initial concept of SBS by the authors in [29], the researchers have proposed various methods to enable SBS. Broadly, the SBS design methodology can be classified into differential [30] [31] or single-ended designs [29][32] [33] [34], current mode [30] [31] or voltage mode transceivers [33][29] [34], or based on channel characteristics such as on-chip [30] [35] or off-chip communication [29] [32]. 3D SICs offer a promising prospect for SBS due to the low channel impedance of the TSVs.…”

Section: Motivation and Prior Workmentioning

confidence: 99%

Reduced Pin-Count Test Strategy for 3D Stacked ICs Using Simultaneous Bi-Directional Signaling Based Time Division Multiplexing

2021

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3D Stacked Integrated Circuits (SICs) offer a promising way to cope with the technology scaling; however, the test access requirements are highly complicated due to increased transistor density and a limited number of test channels. Moreover, although the vertical interconnects in 3D SIC are capable of high-speed data transfer, the overall test speed is restricted by scan-chains that are not optimized for timing. Reduced Pin-Count Testing (RPCT) has been effectively used under these scenarios. In particular, Time Division Multiplexing (TDM) allows full utilization of interconnect bandwidth while providing low scan frequencies supported by the scan chains. However, these methods rely on Uni-Directional Signaling (UDS), in which a chip terminal (pin or a TSV) can either be used to transmit or receive data at a given time. This requires that at least two chip terminals are available at every die interface (Tester-Die or Die-Die) to form a single test channel. In this paper, we propose Simultaneous Bi-Directional Signaling (SBS), which allows a chip terminal to be used simultaneously to send and receive data, thus forming a test channel using one pin instead of two. We demonstrate how SBS can be used in conjunction with TDM to achieve reduced pin count testing while using only half the number of pins compared to conventional TDM based methods, consuming only 22.6% additional power. Alternatively, the advantage could be manifested as a test time reduction by utilizing all available test channels, allowing more parallelism and test time reduction down to half compared to UDS-based TDM. Experiments using 45nm technology suggest that the proposed method can operate at up to 1.2 GHz test clock for a stack of 3-dies, whereas for higher frequencies, a binary-weighted transmitter is proposed capable of up to 2.46 GHz test clock.

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Section: Motivation and Prior Workmentioning

confidence: 99%

Reduced Pin-Count Test Strategy for 3D Stacked ICs Using Simultaneous Bi-Directional Signaling Based Time Division Multiplexing

2021

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“…The idea of SBS was initially reported in [28], following which improved designs capable of delivering up to 900Mbps and 8Gbps (450Mbps and 4Gbps in either direction, respectively) were proposed and tested on fabricated devices in [29] and [30]. While these works rely on voltage-mode signaling, further enhanced design using current-mode differential transceivers were proposed in [31][32] [33] for improved power efficiency in off-chip (chip to chip) [31] [32] as well as on-chip (core to core) [33] signaling. In 3D SICs, SBS through TSVs has different design requirements, primarily because of negligible path resistance when compared to offchip communication.…”

Section: Prior Workmentioning

confidence: 99%

“…To limit the static current, the proposed transmitter is built as an inverter with diode-connected MOSFETs as shown in Fig. 9(a) [31]. The MOSFETs MNS and MPS perform the inverter switching and the diode-connected MOSFETs MNR and MPR serve as active series resistors, minimizing the static current and hence the static power consumption.…”

Section: A Transmittermentioning

confidence: 99%

Test Time Reduction of 3-D Stacked ICs Using Ternary Coded Simultaneous Bidirectional Signaling in Parallel Test Ports

Soomro

Samie

Jennions

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In order to meet the increasing demand for more performance with reduced power consumption and chip formfactor, semiconductor manufacturing is moving towards 3D Stacked Integrated Circuits (SIC). One of the challenges in bringing this technology into realization is the complicated test accessibility requirements of 3D chips, which apart from having adequate defect coverage, should also have minimal test time. A major limiting factor in test time improvement of ICs is the number of chip terminals, such as pins or Through Silicon Vias (TSVs) available for bulk vector transport in testing. In the conventional design, a chip terminal is only used to either send or receive data at any given time. In this paper, a test accessibility architecture based on ternary encoded Simultaneous Bi-Directional Signaling (SBS), intended for use in parallel Test Access Mechanism (TAM) in System on Chip (SoC) based designs, is proposed. This method enables the use of chip terminals to simultaneously send and receive test vectors, effectively doubling the per-pin efficiency during testing. Experiments show that this technique reduces the Overall Test Time (OTT) by up to 53.6% as compared to conventional TAM design methods. Index Terms-3D Stacked Integrated Circuits, System on Chip, Design for Testability, Simultaneous Bi-directional, Test Access Mechanism© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2 the industry by the International Technology Roadmap for Semiconductors (ITRS) [11].In this paper, a novel Test Access Mechanism (TAM) design is proposed for 3D SICs that doubles the data transfer efficiency of the pins and TSVs, resulting in a substantial decrease of the test times. This is achieved by leveraging Simultaneous Bidirectional Signaling (SBS) for full-duplex test mode communication at chip terminals. SBS allows transmission and reception of test bits simultaneously compared to the conventional Uni-Directional Signaling (UDS) scheme in which the signal could travel in only one direction at a given time. Using SBS, a complete transmission and reception channel could be formulated using a single electrical path at the chip terminal instead of two, effectively doubling the number of test-channels and increased parallelism in test scheduling. The paper further discusses the TAM design considerations for the incorporation of SBS in 3D SICs such that it does not interfere with the functional mode performance and standard DFT logic, such as JTAG compliant boundary scan registers. An example implementation suitable for low-frequency test vector transportation is presented, and its electrical characteristics are discu...

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“…Lately, SBTs have been presented over on-chip interconnections. [27][28][29][30][31][32][33] A current-mode SBS for on-chip interconnection is studied in Huang et al, 27 which has overall poor performance. The authors are presented a current-mode differential SBT in Huang et al 28 by utilizing an adaptive impedance-matching structure.…”

Section: Introductionmentioning

confidence: 99%

“…Afterward, a SBS solution has been presented and less than 2-Gbps data rate is attained at the price of increased power consumption. 29 A hybrid circuit topology has been proposed in. 30 The designers are tried to improve the achievable data-rate by employing a MIMO (eight-parallel interconnects and transceivers) architecture.…”

Section: Introductionmentioning

confidence: 99%

A full‐duplex transceiver for 20‐Gbps high‐speed simultaneous bidirectional signaling across global on‐chip interconnections

Jarihani

Sturm

Tonello

2021

Circuit Theory & Apps

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This paper presents a high‐speed simultaneous bidirectional transceiver (SBT) for on‐chip wireline communications. A MOS hybrid transistor is utilized to split the received data from the superimposed signal at both ends of the on‐chip interconnection with the assistance of two drivers, namely main and auxiliary. Moreover, a high‐pass filter (HPF) is used as a differentiator to generate the echo cancelation signal. Consequently, the echo‐cancelation for simultaneous bidirectional signaling (SBS) is realized by the combination of the hybrid device and the differentiator. The proposed SBT has been designed and evaluated using 28‐nm CMOS technology over a narrow 5‐mm on‐chip interconnection, which possesses 11.9‐dB loss at the Nyquist frequency (half a bit rate). The energy‐efficiency of the proposed full‐duplex transceiver (FDT) for 20‐Gbps simultaneous bidirectional data transmission is 0.147 PJ/b/mm. The performance results show that the proposed SBT has better overall performance compared to the previous architectures reported in the literature to date. The layout of the presented SBT occupies a low area of 1574 μm2.

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Differential bidirectional transceiver for on-chip long wires

Cited by 15 publications

References 15 publications

Reduced Pin-Count Test Strategy for 3D Stacked ICs Using Simultaneous Bi-Directional Signaling Based Time Division Multiplexing

Reduced Pin-Count Test Strategy for 3D Stacked ICs Using Simultaneous Bi-Directional Signaling Based Time Division Multiplexing

Test Time Reduction of 3-D Stacked ICs Using Ternary Coded Simultaneous Bidirectional Signaling in Parallel Test Ports

A full‐duplex transceiver for 20‐Gbps high‐speed simultaneous bidirectional signaling across global on‐chip interconnections

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