Differential mode noise modelling and analysis through high‐frequency equivalent circuit of a single‐phase inverter

Abstract

This paper proposes the prediction method of differential mode noise transmitted to the input power of a single‐phase inverter in a high‐frequency model. A high‐frequency equivalent circuit considering the parasitic impedance is proposed. This paper presents a method to measure the parasitic impedance included in the DC link capacitor and insulated‐gate bipolar transistor (IGBT) using a network analyser and extract the parasitic impedance included in the DC bus plate and PCB using Q3D. A mathematical analysis is proposed by applying the double integral Fourier form to the current noise sources, and a method for obtaining differential‐mode noise by analysing the impedance path is proposed. The switching of IGBT is modelled as the noise current source that reflects the pulse width modulation (PWM) duty change using the double integral Fourier form. The impedance path of differential mode noise transmitted to the input is mathematically analysed. The differential mode noise affecting the input is modelled by multiplying the impedance path and the noise source current. The validity of the proposed high‐frequency equivalent circuit and the mathematical analysis is verified by the less than 5% error in the resonant frequency of the derived differential mode noise voltage and the resonant frequency measured experimentally.