Diffusion-rounded CMOS for improving both Ion and Ioff characteristics

Ryu, Myunghwan; Nguyen, Hung Viet; Kim, Young‐Min

doi:10.1587/elex.8.1783

Cited by 2 publications

(1 citation statement)

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“…Many researches have been conducted to model and analyze the diffusion rounding effect [6][7][8]. In this paper, we propose a novel layout approach to achieve a better driving capability and better leakage property by using imperfect diffusion rounding patterning.…”

Section: Introductionmentioning

confidence: 99%

Transistor layout optimization for leakage saving

Ryu

Kang

Kim

2013

2013 International SoC Design Conference (ISOCC)

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In this paper, we investigate electrical effects of transistor layout shape (both in the channel and diffusion) on the performance and leakage current. Through layout optimization techniques, we propose a novel intra-gate biasing technique to reduce leakage current while maintaining drive current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits. Diffusion rounding is another interesting effect which happens due to the imperfect source and drain profile in the sub-wavelength lithography regime. TCAD analysis shows that diffusion rounding at the transistor source side can provide increased I on with decreased I off because of the edge effect. The proposed diffusion-rounded CMOS shows as much as 10% improvement both in the on-current (driving) and the off-current (leakage).

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Section: Introductionmentioning

confidence: 99%