Digital column readout architectures for hybrid pixel detector readout chips

Poikela, T.; Plosila, Juha; Westerlund, Tomi; Buytaert, J.; Campbell, M.; Gaspari, M. De; Llopart, X.; Wyllie, K.; Gromov, V.; Kluit, R.; Beuzekom, M. van; Zappon, Francesco; Zivkovic, V.; Brezina, C; Desch, K.; Fu, Y.; Kruth, A.

doi:10.1088/1748-0221/9/01/c01007

Cited by 13 publications

(14 citation statements)

References 10 publications

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“…Digital circuitry for in-pixel processing becomes a more prominent part in the pixel in terms of area and transistor count. This trend is also visible in pixel readout chips developed as a spin-off for other applications [65][66][67][68][69][70][71][72][73] like photon counting: TABLE II. lists several readout chips, the ones intended for high energy physics (white background) all use enclosed layout except ClicPix_demo [77] where the 65 nm technology provides sufficient radiation tolerance without it, the one for other applications (gray background) do not use enclosed layout except Eiger [72] [73].…”

Section: B Front-end Readout Chipsmentioning

confidence: 87%

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How chips helped discover the Higgs boson at CERN

Snoeys¹

2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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Integrated circuits and devices revolutionized particle physics experiments, and have been a cornerstone in the recent discovery of the Higgs boson by the ATLAS and CMS experiments at the Large Hadron Collider at CERN. Particles are accelerated and brought into collision at specific interaction points. Detectors are giant cameras, about 40 m long by 20 m in diameter, constructed around these interaction points to take pictures of collision products as they fly away from the collision point. They contain millions of channels, often implemented as reverse biased silicon pin diode arrays covering areas of up to 200 m 2 in the center of the experiment, generating a small (~1fC) electric charge upon particle traversals. Integrated circuits provide the readout, and accept collision rates of about 40 MHz with on-line selection of potentially interesting events before data storage. Power consumption directly impacts the measurement quality as it governs the amount of material present in the detector. Radiation tolerance has to exceed space requirements by orders of magnitude. The presence of tens of thousands of chips in a single system requires special attention to uniformity, robustness and redundancy.

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Section: B Front-end Readout Chipsmentioning

confidence: 87%

“…In the newly developed timepix3 chip (Fig. 13) [69] [70], capable of operating with a wide range of gaseous and silicon detectors, the analog part occupies only 25 % of the pixel. It contains a 256 × 256 square pixel-array with 55 µm pitch.…”

Section: B Front-end Readout Chipsmentioning

confidence: 99%

How chips helped discover the Higgs boson at CERN

Snoeys¹

2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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“…However, this method has the disadvantage of high-power consumption, both from distributing the readout clock signal to every register and from clocking at high frequency. This method can be modified to allow a frame-based zerosuppressed readout by adding logic which skips a pixel with no data, and adds a 'flag' which identifies the position of the skipped pixels [15].…”

Section: Pixel Detector Readout Techniquesmentioning

confidence: 99%

“…Several methods such as data node based, network based or a combination of these architectures [16,17] can be used to move packet based, zero-suppressed data from the shift register at one end of the column or matrix to the periphery at the opposite end of the ROIC, and subsequently off-chip. The data are essentially moved from the shift register in one pixel to another, possibly with additional registers per group of pixels to alleviate congestion.…”

Section: Pixel Detector Readout Techniquesmentioning

confidence: 99%

A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree

Fahim

Joshi

Ogrenci-Memik

et al. 2020

IEEE Trans. VLSI Syst.

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A low-power, high-speed arbitration tree for pixel detector readout is presented. The synchronized, binary tree priority encoder establishes a position dependent priority list at the start of every time frame. Pixels that indicate the presence of data for readout, are sequentially granted access to a shared bus for data transfer to the periphery, without the use of an additional global strobe signal. It can be used for either full frame imaging or zero-suppressed readout, in which case it can simultaneously generate the pixel address. To increase the readout frame rate, the pixel array is subdivided into two halves, which allows interleaved latching of data at the output serializer. The design was implemented in a 65 nm LP-CMOS process for the readout of a 64  64 pixel array. Measurement results demonstrate a deadtimeless, full frame imaging rate of ~50 kfps, achieved with a dedicated output for every (32  32) 1024 pixels and for a pixel data packet of 11 bits, with no bit errors detected over 1000 frames. The measured energy per bit is 0.94 pJ.

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“…The detector has 256x256 pixels with a pixel pitch of 55 μm. It allows the acquisition of time and energy information for each incident photon by simultaneously measuring the time-of-arrival (ToA) and time-over-threshold (ToT) of each X-ray photon [36]. The electronics of the Timepix3 chip can be bump bonded to diverse sensor materials such as Si, CdTe, CdZnTe, Ge, or GaAs.…”

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confidence: 99%

Spectral X-ray phase contrast imaging with a CdTe photon-counting detector

Navarrete

Procz²,

Schütz³

et al. 2020

Nuclear Instruments and Methods in Physics Research Section A:

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The present study focuses on the implementation of two X-ray phase contrast imaging (XPCI) techniques: free-space propagation (FSP) and single mask edge illumination (SM-EI) with a microfocus polychromatic X-ray source and a Timepix3 photon-counting detector with a CdTe sensor. This detector offers high spatial resolution, high detection efficiency and it is able to simultaneously record information about Time-over-Threshold (ToT) and Time-of-Arrival (ToA) for each X-ray photon. All these features play a key role in enabling an improvement of XPCI image quality, especially through spectral analysis, since it is possible to measure the energy of each incident X-ray photon. Measurements of phase contrast and contrast-to-noise ratio (CNR) are presented for different energy bins within the typical spectrum of soft X-ray imaging. It is shown that a significant enhancement of XPCI image quality can be obtained, for both implemented techniques, by performing pixel clustering to correct for charge sharing and by introducing some degree of energy-weighting. Keywords. X-ray imaging; Phase-contrast; Photon-counting detector; Timepix; Image quality. Single Mask Edge Illumination (SM-EI) XPCISM-EI is based on the Edge-Illumination principle, originally described by Olivo et al. [23]. In the original set-up, two periodic masks are used: the sample mask, placed before the sample, and the detector mask, located in front of the detector. The sample mask reshapes the incoming beam into smaller beamlets that hit the apertures of the detector mask to create the Edge-Illumination condition, in which only a fraction of the beamlets impinges on the pixel active surface. The detector mask also serves to reduce the smoothing of the phase signal caused by non-ideal pixel Point Spread Functions (PSF) [24]. However, with recent photon-counting devices with a more defined PSF, such as those from the Medipix and Timepix families, the detector mask can be removed and the beamlets aligned with the boundary between two pixels columns (or rows, depending on the mask orientation). This allows for the detection of beam displacement after it traverses the sample, as shown in Fig. 1b [25]. By separating the odd and even pixel columns (or rows), this set-up allows for phase and attenuation signal separation with a single acquisition, since it gives two images with equivalent absorption information but opposite differential phase contrast signals. So long as the PSF is sufficiently sharp [26], the single mask arrangement can provide comparable phase sensitivity to the double-mask configuration, with a tradeoff between resolution and image: the spatial resolution is halved, and the image statistics is doubled. Besides, with a mask design like the one proposed by Krejci et al. [27], in which the beamlets are shaped so they hit the region between four pixels instead of two, the system can be extended to provide 2D sensitivity, even in CT [28]. XPCI with spectral photon-counting detectorsThe development of photon-counting detectors with energy-resolving ca...

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Digital column readout architectures for hybrid pixel detector readout chips

Cited by 13 publications

References 10 publications

How chips helped discover the Higgs boson at CERN

How chips helped discover the Higgs boson at CERN

A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree

Spectral X-ray phase contrast imaging with a CdTe photon-counting detector

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