Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple

Abstract

Abstract-On-chip voltage regulation using distributed Digital Low Drop Out (LDO) voltage regulators has been identified as a promising technique for efficient powermanagement for emerging multi-core processors. Digital LDOs (DLDO) can offer low voltage operation, faster transient response, and higher current efficiency. Response time as well as output voltage ripple can be reduced by increasing the speed of the dynamic comparators. However, the comparator offset steeply increases for high clock frequencies, thereby leading to enhanced variations in output voltage. In this work we explore the design of digital LDOs with multiple dynamic comparators that can overcome this bottleneck. In the proposed topology, we apply time-interleaved comparators with the same voltage threshold and uniform current step in order to accomplish the aforementioned features. Simulation based analysis shows that the DLDO with time-interleaved comparators can achieve better overall performance than variable step algorithm based DLDO in terms of current efficiency, ripple and settling time. For a load step of 50mA, a DLDO with 8 time-interleaved comparators could achieve an output ripple of less than 5mV, while achieving a settling time of less than 0.5us. Load current dependant dynamic adjustment of clock frequency is proposed to maintain high current efficiency of ~97%. keywords-low power, voltage regulation, VLSI, digital, circuit design

A fully integrated digital LDO with voltage peak detecting and push-pull feedback loop control

“…Power management circuit likes LDO is becoming critical to provide a clean and regulated power supply for each individual block in SoCs [1]. LDO can be classified into analog LDO (A-LDO) [2] and digital LDO (D-LDO) [3,4]. Digital LDOs are gaining more attention since they have the advantages of suitable for low operating voltages [3], easy integration, small size, programmability, high stability over a wide range of load current variations and a lower sensitivity to process variations [4].…”

“…LDO can be classified into analog LDO (A-LDO) [2] and digital LDO (D-LDO) [3,4]. Digital LDOs are gaining more attention since they have the advantages of suitable for low operating voltages [3], easy integration, small size, programmability, high stability over a wide range of load current variations and a lower sensitivity to process variations [4]. A baseline discrete-time digital LDO usually consists of a comparator, a serial-in parallel-out bidirectional shift register (S/R), and a P-channel MOSFET (PMOS) array acting as the power transistors [5].…”