Digital lock-detection for systematic phase noise elimination in a phase interpolator CDR

Abstract

A novel solution to eliminating the systematic phase noise in a phase interpolator (PI) clock-to-data recovery (CDR) system was designed and simulated in Simulink. The proposed solution addresses the systematic jitter caused by the bang-bang phase detector using scalable digital logic.

Convenient method of digital PI‐CDR lock‐detection for phase noise elimination and enhanced jitter tolerance

“…3 a . Instead of judging the control code such as [2], the proposed one dealing with the judgment signals of PD produced. Two (N + 1)‐bit shift registers calculate the judgment pulses UP and DN then output Q 0 [N: 0] and Q 1 [N: 0] separately.…”

“…The lock‐detection then turns out to be the key of this measure. Ardalan and Yu [2] gives a theoretic algorithm which based on detecting the control code not to overflow the threshold, which would be complex to realise when the code has too many bits. Moreover, the algorithm did not mention which code should be locked for the best BER.…”

“…1b However, the decrease of the code-update frequency reduces the phase tracking ability of the CDR. Considering a sinusoidal jitter with the frequency f noise and the amplitude Df (means that the peck-to-peak amplitude to be 2Df), the CDR should meet function (2) to ensure the data tracking:…”

“…Therefore the jitter tolerance and the frequency offset tolerance of the CDR are limited by the loop delay. Ardalan and Yu [2] eliminates the systematic phase noise by locking the control code when the CDR is locked. Although it is not mentioned, this method anyway break the coupling between the code-update frequency and the loop delay, which make it possible to get a small phase noise but without sacrificing jitter tolerance ability.…”