Digital multiplier‐less implementation of high‐precision SDSP and synaptic strength‐based STDP

Abstract

Spiking neural networks (SNNs) can achieve lower latency and higher efficiency compared with traditional neural networks if they are implemented in dedicated neuromorphic hardware. In both biological and artificial spiking neuronal systems, synaptic modifications are the main mechanism for learning. Plastic synapses are thus the core component of neuromorphic hardware with on-chip learning capability. Recently, several research groups have designed hardware architectures for modeling plasticity in SNNs for various applications. Following these research efforts, this paper proposes multiplier-less digital neuromorphic circuits for two plasticity learning rules: the spike-driven synaptic plasticity (SDSP) and synaptic strength-based spike timing-dependent plasticity (SSSTDP). The proposed architectures have increased the precision of the plastic synaptic weights and are suitable for spiking neural network architectures with more precise calculations. The proposed models are validated in MATLAB simulations and physical implementations on a field-programmable gate array (FPGA). KEYWORDSFPGA, neuromorphic engineering, plastic synapse, spiking neural network (SNN) Int J Circ Theor Appl. 2020;48:724-738. wileyonlinelibrary.com/journal/cta

Reconfigurable field‐programmable gate array‐based on‐chip learning neuromorphic digital implementation for nonlinear function approximation

“…Moreover, the logic capacity of FPGA to implement complex neural algorithms and prototypes without requiring VLSI chip fabrication makes it a brilliant choice. [19][20][21][22][23][24][25][26][27][28][29][30][31] FPGA-based on-chip learning and off-chip learning, which are sometimes known as online learning and offline learning, are the main methods for learning implementation in the hardware at register transfer level (RTL). 26,27 Motivated by these findings, this paper proposes an efficient and high-speed reconfigurable digital implementation of an SNN using Izhikevich neurons and gradient descent learning on an FPGA to approximate the sigmoid function.…”