Digital Phase‐Locked Loop

Abstract

This chapter overviews the topology of digital phase‐locked loop (DPLL) structure and extensive advantages compared to it analog counterpart, that is, the conventional charge‐pump PLL. The basic operation and implementation of the DPLL building block are introduced, including the digital quantizer, digital embodiment and digitally controlled oscillator. The ‐domain model of the DPLL loop is discussed to provide a high‐level picture how to analyze the digital loop dynamic. To emphasize the feasibility of the potential digital‐signal processing (DSP) techniques embedded in the DPLL architecture, the DSP module is studied with a spur cancellation scheme as a representative example. The rationale of the DSP engine and DPLL implementation with silicon proof is demonstrated to validate the effectiveness of the DSP technique. Finally, multiple state‐of‐the‐art DPLLs (only to name a few because of the length requirement) with various DSP capabilities are reviewed. Those prior works with unprecedentedly performance imply the potential of this digital architecture to be adopted for the integrated circuit design community.