Signals and Communication Technology 2007
DOI: 10.1007/978-3-540-72613-5
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Digital Signal Processing with Field Programmable Gate Arrays

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Cited by 192 publications
(5 citation statements)
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“…Neutron and gamma-ray lobes are well separated from energies above 200 keV. As described above, the developed neutron/gamma-ray discrimination method was implemented to the DNG@NCBJ hardware with use of FPGA for real-time signal processing [19,20].…”
Section: Results Of Signal Processing With Matched Filtering Methodsmentioning
confidence: 99%
“…Neutron and gamma-ray lobes are well separated from energies above 200 keV. As described above, the developed neutron/gamma-ray discrimination method was implemented to the DNG@NCBJ hardware with use of FPGA for real-time signal processing [19,20].…”
Section: Results Of Signal Processing With Matched Filtering Methodsmentioning
confidence: 99%
“…In order to complete the discussion, a possible implementation for one of the proposed SR methods (SSF) is outlined at the end of this paper. The circuitry was developed in Hardware Description Language (HDL) [40] envisaging a straightforward implementation in modern FPGAs.…”
Section: The Sr Algorithmsmentioning
confidence: 99%
“…The signal 𝑟 [𝑛] represents the measured information from a single calorimeter sensor front-end output, after applying the free-running (an uninterrupted) Analog-to-Digital Converter (ADC). A cascade of registers, synchronous with the ADC clock, implements a shift-register structure [40], which is responsible for storing the latest 𝑀 digitized samples. The filter order (𝑀 −1) depends on both the calorimeter reference pulse-shape width and the signal pile-up intensity.…”
Section: Fir Filter Based Energy Estimationmentioning
confidence: 99%
“…In order to complete the discussion, a possible implementation for one of the proposed Sparse Representation methods (in this case, the Separable Surrogate Functional) is outlined at the end of the paper. The circuitry was developed in Hardware Description Language (HDL) [29] envisaging a straightforward implementation in Field-Programmable Gate Array (FPGA) technology [30].…”
Section: The Pile-up Effectmentioning
confidence: 99%
“…The signal 𝑟 [𝑛] represents the measured information from a single front-end calorimeter sensor, after applying the free-running (an uninterrupted) Analog-to-Digital Converter (ADC). A cascade of registers, synchronous with the ADC clock, implements a shift-register structure [30], which is responsible for storing the latest 𝑀 digitized samples. The filter order (𝑀 − 1) depends on both the calorimeter reference pulse-shape width and the signal pile-up intensity.…”
Section: Fir Filter Based Energy Estimationmentioning
confidence: 99%