Digital Tapped Delay Lines for HWIL Testing of Matched Filter Radar Receivers

Abstract

Matched filter processing for pulse compression of phase coded waveforms is a classic method for increasing radar range measurement resolution. A generic approach for simulating high resolution range extended radar scenes in a Hardware in the Loop (HWIL) test environment is to pass the phase coded radar transmit pulse through an RF tapped delay line comprised of individually amplitude-and phase-weighted output taps. In the generic approach, the taps are closely spaced relative to time intervals equivalent to the range resolution of the compressed radar pulse. For a range-extended high resolution clutter scene, the increased number of these taps can make an analog implementation of an RF tapped delay system impractical. Engineers at the U.S. Army Aviation and Missile Research, Development and Engineering Center (AMRDEC) have addressed this problem by transferring RF tapped delay line signal operations to the digital domain. New digital tapped delay line (DTDL) systems have been designed and demonstrated which are physically compact compared to analog RF TDLs, leverage low cost FPGA and data converter technology, and may be readily expanded using open slots in a VME card cage. In initial HWIL applications, the new DTDLs have been shown to produce better dynamic range in pulse compressed range profiles than their analog TDL predecessors. This paper describes the signal requirements and system architecture for digital tapped delay lines. Implementation, performance, and HWIL simulation integration issues for AMRDEC's first generation DTDLs are addressed. The paper concludes with future requirements and plans for ongoing DTDL technology development at AMRDEC.