Digitizer error extraction in the nonlinearity test

Hsieh, L.S.L.; Kumar, Suresh

doi:10.1109/test.1994.528022

Cited by 5 publications

(1 citation statement)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For example, in a manner similar to [21], a model of the nonlinearity introduced by the filter can be created, and its effects can be cancelled in software when, say, the nonlinearity of the circuit under test is being verified.…”

Section: Self Checkingmentioning

confidence: 99%

A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits

Hafed

Abaskharoun

Roberts

2002

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Abstract-An area-efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). Several prototypes were fabricated in a triple-metal 3.3-V 0.35-m CMOS process, and were demonstrated to perform various curve tracing, oscilloscope, and spectrum analysis tasks at a clock rate of 20 MHz (limited by our experimental setup). Designed for 8 bits of quantization, a spurious-free dynamic range (SFDR) of 65 dB at 500 KHz and 61 dB at Nyquist (20.001 MHz) was demonstrated using our prototypes. High-frequency narrow-band signals (extending into the gigahertz range) have been captured through subsampling and the use of a high-bandwidth front-end sampling network. Similarly, circuit phenomena that are broadband in nature were measured by using a delayed-clock subsampling mechanism in which the digitizer sample clock is consistently delayed over multiple runs of the periodic test signal. Delaying the clock is performed using a voltage-controlled delay line tuned by a self-biased delay-locked loop, which allowed for a timing resolution of about one gate delay ( 200 ps). The proposed test core occupies an area equivalent to only about 7000 standard-cell 2-input NAND gates.Index Terms-Automatic test equipment, built-in testing, circuit testing, design for testability, mixed analog-digital integrated circuits.

show abstract

Section: Self Checkingmentioning

confidence: 99%