Diode based gate oxide anti-fuse one time programmable memory array in standard CMOS process

Abstract

A diode based gate oxide anti-fuse one time programmable memory array in standard CMOS process without additional process is presented. The requirements of various components in the anti-fuse cell are discussed. The solution to high voltage reliability problem when programming the gate oxide anti-fuse is provided. Measurement results are performed to confirm the functionality of the design.

Parallel programmable nonvolatile memory using ordinary static random access memory cells

“…However, using dedicated NV memories, such as embedded flash memory, is usually not cost-effective for those chips that require only a small NV capacity for, e.g., chip identification and trimming information storage, since the additional process cost necessary to fabricate the NV memory must be paid for the entire chip area, instead of only the small NV area. For such applications, an NV memory function on a CMOS chip that requires a minimal number of additional process steps [1][2][3][4][5][6][7][8][9][10] is desired. The use of one-time programmable (OTP) memories that do not require additional mask steps for their fabrication is a possible solution to meet such needs, even though the NV data can be programmed only once.…”

“…The use of one-time programmable (OTP) memories that do not require additional mask steps for their fabrication is a possible solution to meet such needs, even though the NV data can be programmed only once. [6][7][8][9][10] In this work, we propose a new type of OTP NV memory, which uses ordinary static random access memory (SRAM) cells as bit cells. Since NV data is automatically recalled into SRAM cells upon each power-up, data transfer from an NV memory to a SRAM becomes unnecessary.…”

Nanomechanical Encoding Method Using Enhanced Thermal Concentration on a Metallic Nanobridge

“…, antifuse and fuse) have been widely used in radio frequency identification (RFID) tags and field-programmable gate array (FPGA) applications because they provide the simplest device architecture, enabling low-cost fabrication, whereas reprogrammed memory technologies require sophisticated device architecture and complex fabrication. , The most commonly used OTP architecture is an antifuse memory device that relies on the breakdown of metal–insulator–metal or diode structures. The main drawback is, however, high leakage power resulting from inherent tunneling current in semiconductor systems. Moreover, its high programming energy, low on/off ratio, operating temperature, and high readout voltage need to be improved to expand its applications.…”

“…29,30 The most commonly used OTP architecture is an antifuse 31 memory device that relies on the breakdown of metal−insulator−metal or diode structures. The main drawback is, however, high leakage power 32 resulting from inherent tunneling current in semiconductor systems. Moreover, its high programming energy, low on/off ratio, operating temperature, and high readout voltage need to be improved to expand its applications.…”