Dipole formation at direct-contact HfO2∕Si interface

Abstract

Direct-contact HfO2∕Si interfaces, which have virtually no interfacial SiO2 layer, exhibit characteristic interface-charge distribution. The authors report that direct-contact interfaces demonstrate a negative flatband-voltage shift that is reduced by the insertion of a ∼0.5-nm-thick Si-oxide layer. The authors propose that the observed flatband-voltage shift is mainly caused by an electrostatic dipole (∼0.5V) formed at the HfO2∕Si interface rather than fixed charges. The effects of the dipole on leakage current are also discussed.

Effect of Annealing Ambient on Structural and Electrical Properties of Ge Metal-Oxide-Semiconductor Capacitors with Pt Gate Electrode and HfO<SUB>2</SUB> Gate Dielectric

“…3(c). Similar behavior was observed by Abe et al, 32) who showed that dipoles at the HfO 2 /Si interface caused by direct contact between HfO 2 and Si led to high leakage currents (on the order of $10 À1 to 10 0 Acm À2 ). Thus, the existence of an IL between the HfO 2 and substrate is required to reliably attain low leakage currents.…”

Optimizing ALD HfO2 for Advanced Gate Stacks with Interspersed UV and Thermal Treatments- DADA and MDMA Variations, Combinations, and Optimization

“…This type of Vfb roll-off has been observed previously. (24)(25)(26)(27)(28) We see no discernable effect on Vfb rolloff from the RTUVO treatments used during this study, other than what can reasonably be attributed to the observed interface layer growth during DUDU processing. Thus, we conclude that RTUVO treatments have little effect on the nature of the HfO 2 /SiO 2 interface.…”

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

“…Changing the ambient surroundings creates oxygen vacancies and band bendings in the oxides which greatly affects their effective work functions. Further more, it is also reported that there is a dipole effects in high-k stacks at both metal/high-k interface and high-k/SiO 2 (or Si) interface [125,[259][260][261], presenting one more uncertainty in the effective work function controlling in MOS devices. These interface properties posing significant challenges in the realization of vacuum work function for the real MOS devices.…”

“…Therefore a special attention should be made to the Fermi level pinning effects in order to select suitable metal gate and the high-k materials for advanced CMOS technologies. It has been shown that adding a capping layer at metal gate/high-k interface or inserting an interlayer at bottom high-k/Si interface by introducing an interfacial dipole can modify the high-k band alignments, therefore obtaining the band-edge work function suitable for both pMOS and nMOS applications [260,261,282].…”