Direct and quantitative evidence for buckling instability as a mechanism for roughening of polymer during plasma etching

Abstract

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Applications of highly non-equilibrium low-pressure oxygen plasma for treatment of polymers and polymer composites on an industrial scale

“…He proposed the existence of a surface film with a structure that differs significantly enough from the structure of a bulk polymer to cause a large mismatch in the stiffness, and thus spontaneous wrinkle formation to minimize the elastic energy. This hypothesis was confirmed by Phaneuf et al [42] for selected conditions. The explanation is feasible for the case in which a polymer is treated in glowing plasma where the samples are subjected to VUV radiation (figure 1) of a penetration depth of the same order as the height of the wrinkles (figure 5).…”

Nanotexturing and Wettability Ageing of Polypropylene Surfaces Modified by Oxygen Capacitively Coupled Radio Frequency Plasma

“…The aspect ratio of the nanofibrils and the separated distance between the nanofibrils further increased at longer oxygen CCP treated time. The nanoscale surface roughness with the corrugation wavelength about 30e70 nm on the polymers by plasma etching had been ascribed to the elastic buckling caused by the ion-induced formation of the highly compressed, modified surface layer [15,16] . The sputtering from the reactor wall also could be favorable to the formation of the nanodots [27] .…”

Two modes of surface roughening during plasma etching of silicon: Role of ionized etch products

“…The precise control of Si etching in Cl-and Br-based plasmas is indispensable for the fabrication of gate electrodes and shallow trench isolation of field effect transistors (FETs) 1,2 through suppressing profile anomalies of sidewalls and bottom surfaces of the feature. 6,7 Atomic-or nanometer-scale roughness on etched feature surfaces of Si has become an important issue to be resolved in the fabrication of nanoscale microelectronic devices, [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26] because the roughness formed during plasma etching would be comparable with the CD and the thickness of the layer being etched and/or the layer underlying; in addition, the nanoscale roughness of etched surfaces of SiO 2 , 21,24,27,28 metal, 22 metal oxide, 22 photoresist, [29][30][31] polymer/polymeric, 26,32,33 and low dielectric constant (low-k) films 21,27,34 has also be an issue of great interest similarly. In gate fabrication, the roughness on feature sidewalls is responsible for the line edge roughness (LER) and line width roughness (LWR), 35,36 which cause the variability in gate or channel length, and thus lead to that in transistor performance.…”