Direct-Conversion WCDMA Transmitter with 163dBc/Hz Noise at 190MHz Offset

Jones, Curtis G.; Tenbroek, Bernard; Fowers, P.; Beghein, Christophe; Strange, Jon; Beffa, Federico; Nalbantis, D.

doi:10.1109/isscc.2007.373431

Cited by 36 publications

(19 citation statements)

References 4 publications

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“…Figure 10.2.1 shows a block diagram of the transceiver in a tri-band WCDMA application. The transmitter is discussed in detail in [6]. The receiver front-end is shown in detail in Fig.…”

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confidence: 99%

“…In the presence of a strong modulated TX blocker at the receiver input the total noise at the output of the receiver consists of four contributions: the IC RX noise figure, the TX noise in the RX band [6], the reciprocal mixing of the TX blocker and the IM2 products arising from the modulated TX blocker. Using the method described in [4] and targeting only a 0.2dB noise-figure degradation at maximum TX power due to reciprocal mixing and IM2 products, then the LNA referred receiver requirement is for an IIP2>+50dBm and LO phase noise <−160dBc/Hz.…”

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confidence: 99%

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Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power Control

Tenbroek¹,

Strange²,

Nalbantis³

et al. 2008

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

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With growing WCDMA adoption there is a strong demand to reduce the cost of WCDMA terminals. Contributing to the relatively high WCDMA terminal cost is the low integration of today's WCDMA radios. Since WCDMA is an FDD system the transmitter and receiver are on simultaneously. A duplexer is used to isolate the receiver from the transmit signal but the isolation of small low-cost duplexers is limited, with a guaranteed isolation at the TX frequency of not more than 52dB. For a Class-3 terminal with 2dB TX path loss due to duplexer and switch, the power at the PA output is +26dBm and the receiver will see a TX leakage of up to −26dBm. Today's state-ofthe-art WCDMA transceivers [1-3] deal with the TX blocking problem by using an external TX SAW filter to eliminate TX noise in the RX band and an external LNA and RX SAW filter to achieve sufficient RX linearity. A typical tri-band transceiver requires 6 SAW filters and 3 LNAs. The tri-band WCDMA transceiver presented here eliminates all external SAW filters and LNAs and achieves excellent performance with standard low-cost duplexers.In the presence of a strong modulated TX blocker at the receiver input the total noise at the output of the receiver consists of four contributions: the IC RX noise figure, the TX noise in the RX band [6], the reciprocal mixing of the TX blocker and the IM2 products arising from the modulated TX blocker. Using the method described in [4] and targeting only a 0.2dB noise-figure degradation at maximum TX power due to reciprocal mixing and IM2 products, then the LNA referred receiver requirement is for an IIP2>+50dBm and LO phase noise <−160dBc/Hz. The presence of a CW blocking signal together with the TX signal will produce an in-band spurious response when this blocking signal is either at 0.5× or 2.0× the duplex frequency. To achieve sufficient margin against the requirements [7] an IIP3 of −5dBm is targeted. Figure 10.2.1 shows a block diagram of the transceiver in a tri-band WCDMA application. The transmitter is discussed in detail in [6]. The receiver front-end is shown in detail in Fig. 10.2.2. A singleended LNA is used to interface to standard single-ended duplexers. The LNA has a high IP3 common-source input stage, cascode gain control and a notch filter at the source of the cascode. A low-noise Qenhancement circuit is used to improve notch selectivity. Together with the LC load this notch filter provides additional attenuation of the TX leakage. The LNA is followed by a high IP3 transconductor and a passive mixer optimized for high IP2. A low-pass filter is inserted between the passive mixer and the transimpedance amplifier to further improve out-of-band IP3. The transimpedance amplifier also implements the first real pole of a 5 th -order baseband filter. The remaining 4 poles are implemented as two biquads, and a 1 st -order equalizer is added to reduce group-delay variation as shown in Fig. 10.2.1. The overall baseband filter response is optimized for minimum ripple and group-delay variation to maintain low EVM for HSDPA applicat...

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“…Figure 10.2.1 shows a block diagram of the transceiver in a tri-band WCDMA application. The transmitter is discussed in detail in [6]. The receiver front-end is shown in detail in Fig.…”

mentioning

confidence: 99%

mentioning

confidence: 99%

Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power Control

Tenbroek¹,

Strange²,

Nalbantis³

et al. 2008

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

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“…The transmitter in [16] uses an LO generation scheme along with auto-calibration to reduce the noise of the mixer. In the transmitter of [17], a feedback cancellation method is employed to suppress the noise of the on-chip diver.…”

Section: Transmitter Designmentioning

confidence: 99%

4<sup>th</sup> generation wireless transceiver design

Larson

Asbeck

Kimball

2010

2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

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“…To enable cost-effective SAW-less FDD in modern communication standards such as LTE, the transmitter has to achieve ever more stringent requirements, such as extremely low out of-band-noise [2] and C-IM3 [3]. Fortunately, the speed of nanoscale CMOS is now sufficient to enable a new kind of transmitters, the cartesian Direct Digital RF Modulators (DDRM), which bring the digital-to-analog conversion directly to the antenna [4].…”

Section: Introductionmentioning

confidence: 99%

A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and −58dBc C-IM3

Ingels

Zhang

Raczkowski

et al. 2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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This paper presents a 1.2-2.6GHz 2x12 bit Direct Digital RF Modulator (DDRM) realized in 28nm CMOS. The digital cartesian transmitter features baseband sampling speeds up to LO. The intrinsically linear architecture features currentmode operation at 25% duty cycle, which requires less predistortion than existing digital transmitters. The applied digital intensive LO modulation reduces the power consumption of the LO distribution. Except for the output stage at 1.8V, the modulator is powered from 0.9V supply. The DDRM features an OP1dB of 15.5dBm. At 3.9dBm output power, the un-calibrated C-IM3 is better than -42dBc, while the image is below -49dBc. With a simple 1D calibration the C-IM3 can easily be improved to below -58dBc. The modulator's peak drain efficiency at 17.5dBm is 34%.

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Direct-Conversion WCDMA Transmitter with 163dBc/Hz Noise at 190MHz Offset

Cited by 36 publications

References 4 publications

Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power Control

Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power Control

4<sup>th</sup> generation wireless transceiver design

A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and −58dBc C-IM3

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Direct-Conversion WCDMA Transmitter with 163dBc/Hz Noise at 190MHz Offset

Cited by 36 publications

References 4 publications

Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power Control

Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power Control

4<sup>th</sup> generation wireless transceiver design

A linear 28nm CMOS digital transmitter with 2&#x00D7;12bit up to LO baseband sampling and &#x2212;58dBc C-IM3

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Resources

About

A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and −58dBc C-IM3