Direct copper electrodeposition on a chemical vapor-deposited ruthenium seed layer for through-silicon vias

Shi, Peng; Enloe, Jack; Boom, Ruud van den; Sapp, Brian

doi:10.1109/iitc.2012.6251644

Cited by 8 publications

(5 citation statements)

References 3 publications

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“…In this section, we will demonstrate the capability of Atotech's chemistry for direct plating of Cu on Ru seeded high AR TSVs across the wafer. The chemistry containing Spherolyte Leveller 10 is able to generate a nucleation density greater than 10 12 cm -2 [3].…”

Section: Full Wafer Direct Cu Plating On 2×40 µM Tsvsmentioning

confidence: 99%

Direct Cu plating of high aspect ratio through silicon vias (TSVs) with Ru seed on 300 mm wafer

Wafula

Pattanaik

Enloe

et al. 2014

IEEE International Interconnect Technology Conference

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In this paper, physical and electrical results of full wafer direct Cu plating of 2×40 µm TSVs with thin Ru seed are presented. Physical vapor deposition of about 100 nm Cu in the field is shown to improve plating non-uniformity across the structured wafer. TSV plating using Atotech's TSV III chemistry results in bottom-up growth with strong TSV sidewall suppression and void free TSV fill. Early results for in-line electrical test and voltage ramp dielectric breakdown reliability testing are discussed. INTRODUCTIONHigh-aspect ratio TSVs are desirable for 3D-IC integration with increased device density and smaller keepout zones. Good step coverage of thin film barrier and seed for such TSVs becomes increasingly challenging when TSVs exceed a depth to diameter ratio of 15:1. Traditional physical vapor deposition (PVD) techniques fail to yield uniform coverage. Hence chemical vapor deposition (CVD) or atomic layer deposition (ALD) based barrier and seed layers have been adopted. A conducting seed is a prerequisite for the electrodeposition of Cu, which is so far the preferred method for TSV metallization. Ru has been widely considered as a seed layer for Cu electrodeposition in high aspect ratio BEOL and 3DI structures [1, 2], with added advantage due to its barrier properties. To reduce cost of ownership, a thin Ru seed layer is desirable, which in turn results in an increased challenge to Cu electrodeposition due to the higher electrical resistance of the thin Ru layer.In this report, a study of electroplating high aspect ratio TSVs (depth to diameter aspect ratio of 20:1) with Ru seed layer on 300 mm wafers is presented. A field-only PVD copper film of optimized thickness is used to demonstrate void-free bottom-up TSV filling, mitigating the terminal effect in plating across the wafer. This study also presents TSV in-line electrical test and early reliability results.

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Section: Full Wafer Direct Cu Plating On 2×40 µM Tsvsmentioning

confidence: 99%

Direct Cu plating of high aspect ratio through silicon vias (TSVs) with Ru seed on 300 mm wafer

Wafula

Pattanaik

Enloe

et al. 2014

IEEE International Interconnect Technology Conference

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“…Hence, the stability of the interconnect system is also an issue of electronic packaging. Through-silicon via (TSV) is the main interconnect architecture in 3D integrated circuit packaging, and the current mainstream TSV is fabricated with electroplated copper (Cu) [ 6 , 7 , 8 , 9 , 10 , 11 ]. Protrusion and thermal stress are the major mechanical reliability issues in TSV.…”

Section: Introductionmentioning

confidence: 99%

Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique

Huang

Lee

2021

Materials

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Stress-induced performance change in electron packaging architecture is a major concern when the keep-out zone (KOZ) and corresponding integration density of interconnect systems and transistor devices are considered. In this study, a finite element analysis (FEA)-based submodeling approach is demonstrated to analyze the stress-affected zone of through-silicon via (TSV) and its influences on a planar metal oxide semiconductor field transistor (MOSFET) device. The feasibility of the widely adopted analytical solution for TSV stress-affected zone estimation, Lamé radial stress solution, is investigated and compared with the FEA-based submodeling approach. Analytic results reveal that the Lamé stress solution overestimates the TSV-induced stress in the concerned device by over 50%, and the difference in the estimated results of device performance between Lamé stress solution and FEA simulation can reach 22%. Moreover, a silicon–germanium-based lattice mismatch stressor is designed in a silicon p-type MOSFET, and its effects are analyzed and compared with those of TSV residual stress. The S/D stressor dominates the stress status of the device channel. The demonstrated FEA-based submodeling approach is effective in analyzing the stress impact from packaging and device-level components and estimating the KOZ issue in advanced electronic packaging.

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“…[1][2][3][4][5][6][7] Ru has been widely investigated as good adhesion layer to Cu for its low resistance and capability of direct electroplating of Cu. 2,3,8 However, it is rather challenging to polish Ru since it would form toxic RuO 4 in the acid slurry; also the high potential difference between the Ru and Cu would result in the galvanic corrosion in the process of chemical mechanical polishing (CMP). 9 Co has shown good properties as Cu capping layer or adhesion layers.…”

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confidence: 99%

Direct Copper Plating on Ultra-Thin Sputtered Cobalt Film in an Alkaline Bath

et al. 2013

J. Electrochem. Soc.

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We report on the electrochemical process and nucleation mechanism of the “direct-on-barrier” electroplating of copper on ultrathin cobalt adhesion layer from an alkaline CuSO4 and ethylenediamine (En) bath without additives. Results show that the corrosion current density was much lower in the alkaline bath than that in the commercial acidic bath due to formation of the CuEn22+ species in the aqueous CuSO4-En solution. The CuEn22+ species can well stop the reaction between the copper ions and Co by reducing the potential of copper ions. The current-time transients were not typical of a diffusion-limited nucleation and growth. Pure instantaneous or progressive nucleation of copper on Co layer was not observed. The impact of current density on the orientation, resistance and morphology was studied. Copper film in 250 nm thick was successfully deposited on the 10 nm Co film in the patterned wafers. And Cu was electroplated onto ultrathin Co layer with ∼5 nm thickness and TEM result shows that there is no obvious Co thickness loss.

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Direct copper electrodeposition on a chemical vapor-deposited ruthenium seed layer for through-silicon vias

Cited by 8 publications

References 3 publications

Direct Cu plating of high aspect ratio through silicon vias (TSVs) with Ru seed on 300 mm wafer

Direct Cu plating of high aspect ratio through silicon vias (TSVs) with Ru seed on 300 mm wafer

Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique

Direct Copper Plating on Ultra-Thin Sputtered Cobalt Film in an Alkaline Bath

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