Direct Digital Synthesis: A Tool for Periodic Wave Generation

Lyons, Richard G.

doi:10.1002/9780470170090.ch21

Cited by 12 publications

(5 citation statements)

References 17 publications

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“…A DDS must meet the requirement of its SFDR. Techniques for Spur reduction and therefore SFDR improvement have been discussed in [4,5]. However these suggested techniques significantly increase the noise floor (> 60 dB) which is not acceptable.…”

Section: Figure 2 Taylor Dds Block Diagram [3]mentioning

confidence: 95%

On Hartley Image rejection receivers and adaptive sinusoidal interference cancellation in automotive wireless links

Mazumdar

Kadambi

Rashid

et al. 2014

17th International IEEE Conference on Intelligent Transportation Systems (ITSC)

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Spurious-free Dynamic Range (SFDR) of frequency sources such as local oscillators in radio has a profound effect on the minimum signal strength that can be detected. Greater the level of unwanted spurs the more difficult it is to detect an incoming signal in the presence of existing interferers and minimum signal/noise ratio at the demodulator input. Taylor series based Direct Digital Synthesis (DDS) produces an SFDR of around 74dB. The proposed architectures in this paper attempt to improve the SFDR by using a Hartley Image suppressor and using a adaptive sinusoidal interference canceller. The resultant improvement in SFDR is around 45 dB by using the Hartley image suppressor and 40dB using the adaptive interference canceller. The two proposed spur suppression techniques are compared in terms of dynamic power, realized noise floor and hardware complexity.

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Section: Figure 2 Taylor Dds Block Diagram [3]mentioning

confidence: 95%

On Hartley Image rejection receivers and adaptive sinusoidal interference cancellation in automotive wireless links

Mazumdar

Kadambi

Rashid

et al. 2014

17th International IEEE Conference on Intelligent Transportation Systems (ITSC)

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“…In our designs, we use the principle of DDS for carrier generation on the FPGA board [6][7][8]. The two popular methodologies for carrier generation are discussed in [6].…”

Section: Principle Of Ddsmentioning

confidence: 99%

“…This is shown in Fig. 10, where we use an 8-bit adder and a multiplexer whose select signal being y3=∑ (4,5,6,7). For the symbols 8, 9, 10 and 11, we rotate the QPSK constellation by j = −22.5°which is equivalent to subtracting a decimal value of d = 16 from the ROM address bus of QPSK modulator.…”

Section: Modulatormentioning

confidence: 99%

High‐performance VLSI architectures for M‐PSK modems

Mamidala

Dhar

2017

IET Circuits, Devices & Systems

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M-PSK (phase shift keying) modulation schemes are used in many high-speed applications like satellite communication, as they are more bandwidth and power efficient compared with other schemes. This study presents very large scale integrated circuits (VLSI) architectures for modulators and demodulators of quadrature phase shift keying (QPSK), 8PSK and 16PSK systems, based on the principle of direct digital synthesis. The proposed modulators do not use any multiplier in contrast to the conventional modulators and hence they are relatively fast and area efficient. Based on the coherent detection technique, this study proposes new demodulation algorithms for 8PSK and 16PSK systems which can be implemented both in analogue and digital domains. This study also presents VLSI architectures for all the proposed algorithms. The proposed architectures are described in Verilog and implemented on Xilinx field programmable gate arrays (FPGAs). The simulation results verify their functional validity and implementation results show the suitability of the proposed architectures for satellite communications.

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“…Techniques for saving memory resources are described in the literature (see [20] for more details). It is important to remark that the waveform with the lowest Doppler frequency generated by the sinusoid generator determines the frequency resolution that can be achieved by using LUT.…”

Section: Piecewise Polynomial Approximationmentioning

confidence: 99%

An Accurate Hardware Sum-of-Cisoids Fading Channel Simulator for Isotropic and Non-Isotropic Mobile Radio Environments

Vela-Garcia

Castillo

Parra-Michel

et al. 2012

Modelling and Simulation in Engineering

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The rapid technological development in the field of wireless communications calls for devices capable of reproducing and simulating the behavior of the channel under realistic propagation conditions. This paper presents a hardware fading channel simulator that is able to generate stochastic processes characterized by symmetrical and asymmetrical Doppler power spectral densities (PSDs) depending on the assumption of isotropic or non-isotropic scattering. The concept of the proposed hardware simulator is based on an implementation of the sum-of-cisoids (SOC) method. The hardware simulator is capable of handling any configuration of the cisoid's amplitudes, frequencies, and phases. Each of the cisoids that constitutes the SOC model is implemented using a piecewise polynomial approximation technique. The investigation of the higher-order statistics of the generated fading processes, like the level-crossing rate (LCR) and the average duration of fades (ADF), shows that our design is able to reproduce accurately the key features of realistic channel models that are considered as candidates for the latest wireless communication standards.

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Direct Digital Synthesis: A Tool for Periodic Wave Generation

Cited by 12 publications

References 17 publications

On Hartley Image rejection receivers and adaptive sinusoidal interference cancellation in automotive wireless links

On Hartley Image rejection receivers and adaptive sinusoidal interference cancellation in automotive wireless links

High‐performance VLSI architectures for M‐PSK modems

An Accurate Hardware Sum-of-Cisoids Fading Channel Simulator for Isotropic and Non-Isotropic Mobile Radio Environments

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