Direct optimization of a PCI express link equalization in industrial post-silicon validation

Abstract

Post-silicon validation is a crucial industrial testing process in modern computer platforms. Post-silicon validation of high-speed input/output (HSIO) links can be critical for making a product release qualification. Peripheral component interconnect express (PCIe) is a high-performance interconnect architecture widely adopted in the computer industry, and one of the most complex HSIO interfaces. PCIe data rates increase on every new generation. To mitigate channel effects due to the increase in transmission speeds, the PCIe specification defines requirements to perform equalization (EQ) at the transmitter (Tx) and at the receiver (Rx). During the EQ process, one combination of Tx/Rx EQ coefficients must be selected to meet the performance requirements of the system. Testing all possible coefficient combinations is prohibitive. Current industrial practice consists of finding a subset of combinations at post-silicon validation using maps of EQ coefficients, which are obtained by measuring the eye height, eye width, and the eye asymmetries of the received signal. Given the large number of electrical parameters and the multiplicity of signal eyes that are produced by on-die probes for observation, finding this subset of coefficients is often a challenge. In order to overcome this problem, a direct optimization method based on a suitable objective function formulation to efficiently tune the Tx and Rx EQ coefficients to successfully comply with the PCIe specification is presented in this report. The proposed optimization approach is based on a low-cost computational procedure combining pattern search and Nelder-Mead methods to efficiently solve an objective function with many local minima, and evaluated by lab measurements on a realistic industrial postsilicon validation platform.

A Multi-Stage CTLE Design and Optimization for PCI Express Gen6.0 Link Equalization

“…The final version is available at http://dx.doi.org/10.1109/LAEDC58183.2023.10209113 received coefficients setting to its Tx EQ circuitry. This process of computing the coefficients, communicating them to the Tx, and checking the signal quality can be repeated multiple times until the required BER is achieved [5], [6].…”

“…To have a unity gain for the Tx equalizer, the Tx coefficients are subject to the following protocol constraints (as per the PCIe specification [6]):…”

“…An initial optimization problem can be defined through a constrained formulation, * arg min ( ) u = x xx (11) subject to elinearity(x) > 0.85 and VEC(x) < 6dB, where u(x) is the total area of the PAM4 eye diagram, Additionally, we need to ensure the optimal system response is within a suitable area in the coefficients search space of the EQ map. Here we follow our work in [6] and [11] to redefine the corresponding objective function. The four responses around u'(x * ) must be at least 80% of the value of u'(x * ), as shown in Fig.…”

Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation

“…In [22], we propose a simple yet efficient optimization methodology to find the optimal subset of coefficients for the Tx and Rx in a PCIe equalization process, here summarized.…”

“…Eye diagram results: comparing the proposed methodology (Rf(x*)) against the initial design (Rf(x0) ) and the exhaustive method (Rf(x*exhaustive)). From[22].…”