Direct Statistical Simulation of Timing Properties in Sequential Circuits

Abstract

Abstract. Accurate timing analysis of digital integrated circuits is becoming harder to achieve with current and future CMOS technologies. The shrinking feature sizes lead to increasingly important local process variations (PV), making existing methods like corner-based static timing analysis (STA) yield overly pessimistic results. In this paper we propose a general purpose statistical circuit simulator for accurate timing analysis. A statistical simplified transistor model (SSTM) is used as the simulator's building block, allowing accurate simulation of sequential circuits while fast statistical analysis is achieved by solving a system of random differential equations (RDE), thus avoiding time-consuming Monte Carlo simulations. The conducted experiments show the accurate calculation of crossing time statistical moments for several sequential cells using 45 nm CMOS technology.

Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver

“…The RDEM method is applied to the following three different sequential circuits with increasing level of complexity [51] The load capacitance (C L ) is changed from 10 fF to 25 fF for different scenarios. All the delay mean errors are within 1% of SpectreB MC simulations, except DLH X1 that has a −2.86% maximum mean error, as can be seen in Table III.…”