Discerning the dominant out-of-order performance advantage

McFarlin, Daniel S.; Tucker, C.; Zilles, Craig

doi:10.1145/2451116.2451143

Cited by 32 publications

(9 citation statements)

References 58 publications

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“…In their work, McFarlin et al concluded that the performance advantage of OoO processors against statically scheduled architectures mainly comes from the ability to speculate aggressively [30]. Their experimental study shows that, by replaying dominant schedules as if they were static schedules, the execution can reach 80% of the performance of normal OoO.…”

Section: A Toward Continuous Optimizationsmentioning

confidence: 99%

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

Rokicki

Rohou²,

Derrien³

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In order to provide dynamic adaptation of the performance/energy trade-off, systems today rely on heterogeneous multi-core architectures (different micro-architectures on a chip). These systems are limited to single-ISA approaches to enable transparent migration between the different cores. To offer more trade-off, we can integrate statically scheduled microarchitecture and use Dynamic Binary Translation (DBT) for task migration. However, in a system where performance and energy consumption are a prime concern, the translation overhead has to be kept as low as possible. In this paper we present Hybrid-DBT, an open-source, hardware accelerated DBT system targeting VLIW cores. Three different hardware accelerators have been designed to speed-up critical steps of the translation process. Experimental study shows that the accelerated steps are two orders of magnitude faster than their software equivalent. The impact on the total execution time of applications and the quality of generated binaries are also measured.

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Section: A Toward Continuous Optimizationsmentioning

confidence: 99%

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

Rokicki

Rohou²,

Derrien³

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Although these groups are superficially similar to atomic blocks, they are not saved, specialized, or reused, as our atomic blocks are. Instruction scheduling memoization: McFarlin et al [36] demonstrate that most of out-of-order execution's benefit comes from its ability to use a speculative execution schedule, but not necessarily a different schedule for every instance of an instruction sequence. This is similar to our observation that many static regions of code have stable instruction schedules.…”

Section: Related Workmentioning

confidence: 99%

The heterogeneous block architecture

Fallin¹,

Wilkerson

Mutlu³

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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This paper makes two new observations that lead to a new heterogeneous core design. First, we observe that most serial code exhibits fine-grained heterogeneity: at the scale of tens or hundreds of instructions, regions of code fit different microarchitectures better (at the same point or at different points in time). Second, we observe that by grouping contiguous regions of instructions into blocks that are executed atomically, a core can exploit this heterogeneity: atomicity allows each block to be executed independently on its own execution backend that fits its characteristics best.Based on these observations, we propose a fine-grained heterogeneous design that combines heterogeneous execution backends into one core. Our core design, the heterogeneous block architecture (HBA), breaks the program into blocks of code, determines the best backend for each block, and specializes the block for that backend. As an initial, concrete design, we combine out-of-order, VLIW, and in-order backends, using simple heuristics to choose backends. We compare HBA to multiple baseline core designs (including monolithic out-of-order, clustered out-of-order, in-order and a state-of-the-art heterogeneous core design) and show that HBA can provide significantly better energy efficiency than all designs at similar performance. Averaged across 184 traces from a wide variety of workloads, HBA reduces core power by 36.4% and energy per instruction by 31.9% compared to a 4-wide out-of-order core. We conclude that HBA provides a flexible substrate for exploiting fine-grained heterogeneity, enabling new energy-performance tradeoff points in core design.

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“…Those less familiar with dynamic scheduling might consult some early descriptions of dynamically scheduled processors [7], [8], more recent designs [9], and a study of the inherent differences between static and dynamic designs [10]. The front end of the core is responsible for fetching, decoding, and enqueuing an instruction for execution, a process which takes several cycles and which here will be referred to as fetch/ decode; see Figure 1.…”

Section: A Dynamically Scheduled Processorsmentioning

confidence: 99%

Discovering Barriers to Efficient Execution, Both Obvious and Subtle, Using Instruction-Level Visualization

Koppelman

Michael

2014

2014 First Workshop on Visual Performance Analysis

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Abstract-CPU performance is determined by the interaction between available resources, microarchitectural features, the execution of instructions, and by the data. These elements can interact in complex ways, making it difficult for those seeing only aggregate performance numbers, such as miss ratios and issue rates, to determine whether there are reasonable avenues for performance improvement. A technique called instructionlevel visualization helps users connect these disparate elements by showing the timing of the execution of individual program instructions. The PSE visualization program enhances instructionlevel visualization by showing which instructions contribute to execution inefficiency in a way that makes it easy to locate dependent instructions and the history of events affecting the instruction. A simple annotation system makes it easy for a user to attach custom information. PSE has been used for microarchitecture research, simulator debugging, and for instructional use.

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Discerning the dominant out-of-order performance advantage

Cited by 32 publications

References 58 publications

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW

The heterogeneous block architecture

Discovering Barriers to Efficient Execution, Both Obvious and Subtle, Using Instruction-Level Visualization

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