Discrete-time parametric amplification based on a three-terminal mos varactor: analysis and experimental results

Ranganathan, S.; Tsividis, Y.

doi:10.1109/jssc.2003.819162

Cited by 63 publications

(32 citation statements)

References 3 publications

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“…Low-gain voltage amplification, e.g., to implement a 1.5-bit MDAC, can be achieved by using the parametric MOS structure described in [13], where a discrete-time (DT) MOS parametric amplifier (MPA) was experimentally evaluated for the first time. In this amplifier, the gain is set by varying the total equivalent gate capacitance of a single MOSCAP device, while maintaining the total gate charge between the sampling phase U 1 and the amplification phase U 2 .…”

Section: Parametric Amplificationmentioning

confidence: 99%

Low-Power, High-Speed and High-Effective Resolution Pipeline Analog-to-Digital Converters in Deep Nanoscale CMOS

Goes

Pereira

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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This chapter reviews recent advances in low-power design techniques for high-speed and high-effective resolution pipeline Analog-to-Digital Converters (ADCs). The advantages of replacing, in a pipeline ADC architecture, the traditional local low-resolution parallel (flash) quantizers by low-resolution successiveapproximation register (SAR) ADCs are shown through a set of selected works. Some of the most promising energy-efficient residue amplification techniques are reviewed, spanning from open-loop and closed-loop amplifierless approaches to innovative and highly-scalable amplifier-based topologies.

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Section: Parametric Amplificationmentioning

confidence: 99%

Low-Power, High-Speed and High-Effective Resolution Pipeline Analog-to-Digital Converters in Deep Nanoscale CMOS

Goes

Pereira

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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“…The needed MBTA in 1.5-bit stages of pipeline ADC can be achieved by using the parametric MOS amplification described in [8,9] where a discrete-time amplifier was evaluated. In this amplifier, the gain is set through the reduction of the total equivalent gate capacitance of a single MOSCAP device, while maintaining the total gate charge between the sampling and the amplification phase.…”

Section: Low-gain Amplification Using a Mos Capacitormentioning

confidence: 99%

“…In this amplifier, the gain is set through the reduction of the total equivalent gate capacitance of a single MOSCAP device, while maintaining the total gate charge between the sampling and the amplification phase. As explained in [8,9], the capacitance reduction of a MOSCAP can be achieved by moving it from inversion into depletion, as result of changing the control voltage (V control ) applied to the drain from the The amplifier circuit operates as follows. During phase Ф 1 the input signal is sampled by M 1a -M 1b and a corresponding charge is stored.…”

Section: Low-gain Amplification Using a Mos Capacitormentioning

confidence: 99%

“…C ox is the total gate-oxide capacitance and C gb is the gate-bulk capacitance during the amplification phase [9]. The main differences of the basic MOSCAP structure used here from the one used in [8,9] lies on the fact that 2 halfsized MOSCAPs are used instead of a single one and, on the other hand, their short-circuited sources are left floating.…”

Section: Low-gain Amplification Using a Mos Capacitormentioning

confidence: 99%

“…The main differences of the basic MOSCAP structure used here from the one used in [8,9] lies on the fact that 2 halfsized MOSCAPs are used instead of a single one and, on the other hand, their short-circuited sources are left floating.…”

Section: Low-gain Amplification Using a Mos Capacitormentioning

confidence: 99%

See 2 more Smart Citations

New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification

Oliveira

Goes

Paulino

et al. 2008

2008 15th IEEE International Conference on Electronics, Circuits and Systems

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-In this paper a new time-interleaved 1.5-bit MDAC circuit is proposed. This circuit is well suited to be used in ultra low-power high-speed 4-to-8 bits pipeline ADCs. The required gain of two is implemented by switching a MOS capacitor from inversion into depletion within a clock-cycle. Low-power is achieved since no operational amplifiers are required but, instead, simple source-followers are used. Simulation results of a complete front-end stage of a 6-bit 2-channel pipeline ADC demonstrate the efficiency of the proposed technique.

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Parametric CMOS upconverters and downconverters

Zhao

Magierowski

Belostotski

2013

Circuit Theory & Apps

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SUMMARYThis paper discusses parametric CMOS mixers as potential radio-frequency front-end contributors to advanced mm-wave and sub-mm-wave wireless communicators. It outlines fundamental concepts underlying parametric circuit operation highlighting its benefits with regards to power consumption, speed, and noise performance. The implementation of parametric CMOS architectures is detailed. Critical device properties and figures of merit are shown. Measurement results of prototype designs are given.

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Discrete-time parametric amplification based on a three-terminal mos varactor: analysis and experimental results

Cited by 63 publications

References 3 publications

Low-Power, High-Speed and High-Effective Resolution Pipeline Analog-to-Digital Converters in Deep Nanoscale CMOS

Low-Power, High-Speed and High-Effective Resolution Pipeline Analog-to-Digital Converters in Deep Nanoscale CMOS

New low-power 1.5-bit time-interleaved MDAC based on MOS capacitor amplification

Parametric CMOS upconverters and downconverters

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