Discrete wavelet transform: data dependence analysis and synthesis of distributed memory and control array architectures

Handling large-size discrete wavelet transform on network-based computing systems — parallelization via divisible load paradigm

“…Therefore, a number of studies relating to computational optimizations and parallel processing of the DWT have been carried out. Examples of such works include [5,13,10,8].…”

Parallel Wavelet Transform over Distributed Computer Network for Real–Time Applications

“…The algorithms can be implemented in SIMD, MIMD and pipeline architectures on the configured system. Other works on implemented wavelet transform and coding are restricted to expensive hardware [1], expensive and fast network architectures [2], or involves transputer systems making the programming very complex [3]. Our system is more robust in terms of implementation and highly effective in the transform representation for distributed computing applications.…”

Highly efficient high-speed/low-power architectures for the 1-D discrete wavelet transform

“…Therefore, the implementation of the DWT by means of dedicated VLSI application-specific integrated circuits has recently captivated the attention of a number of researchers, and many DWT architectures have already been proposed [12]- [25]. Some of these devices have been targeted to have a low hardware complexity, but they require at least 2 clock cycles (ccs) to compute the DWT of a sequence having samples (e.g., the devices proposed in [12]- [14], the architecture A2 in [15], etc.). Nevertheless, also a large number of devices, having a period of approximately ccs, has been designed (e.g., the three architectures in [14] when they are provided with a doubled hardware, the architecture A1 in [15], the architectures in [16]- [18], the parallel filter in [19], etc.).…”

“…Some of these devices have been targeted to have a low hardware complexity, but they require at least 2 clock cycles (ccs) to compute the DWT of a sequence having samples (e.g., the devices proposed in [12]- [14], the architecture A2 in [15], etc.). Nevertheless, also a large number of devices, having a period of approximately ccs, has been designed (e.g., the three architectures in [14] when they are provided with a doubled hardware, the architecture A1 in [15], the architectures in [16]- [18], the parallel filter in [19], etc.). Most of these architectures exploit the recursive pyramid algorithm (RPA) [26] or similar scheduling techniques in order both to reduce memory requirement and to employ only one or two filter units, independently from the number of decomposition levels to be computed.…”