Distinguishing Resistive Small Delay Defects from Random Parameter Variations

Qian, Xi; Singh, A.D.

doi:10.1109/ats.2010.62

Cited by 26 publications

(13 citation statements)

References 21 publications

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“…This property could be more difficult to accomplish for some advanced technologies. More recently Qian and Singh [14] have proposed a test strategy to distinguish resistive small delay defects from random parameter variations. They propose to observe the relative change to switching delay of the slow path with variation in the power supply voltage.…”

Section: Introductionmentioning

confidence: 99%

Screening small-delay defects using inter-path correlation to reduce reliability risk

Garcia-Gervacio

Nocua

Champac

2015

Microelectronics Reliability

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Section: Introductionmentioning

confidence: 99%

Screening small-delay defects using inter-path correlation to reduce reliability risk

Garcia-Gervacio

Nocua

Champac

2015

Microelectronics Reliability

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“…After generating the discrete open resistance set (line 1), the procedure starts in the first part by fault simulating all fault locations (ROF s), test patterns (T P s) using V DD settings (V DDs) and open resistance values (ROs) to obtain the path delay information (P D) as shown in lines (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18). Once the delay values (P D) for fault free paths (∀RO = 0) and faulty paths (∀RO ∈ ROs) are obtained, the longest path delays at each V DD of long paths (LP D G (V DD)) considering (T P ∈ T P s G ) and of short paths (LP D S (V DD)) considering (T P ∈ T P s S ) are identified using the fault free path delay data P D (∀RO = 0) as shown in line [19][20][21][22].…”

Section: Fig 7 Prior Spectre Simulationmentioning

confidence: 99%

“…Additionally, ROF detectability with V DD is presented in Table IV columns [5][6][7][8][9][10]. The open resistance detection threshold is presented for small delays in columns 5-7 and gross delay faults in columns 8-10.…”

Section: Experimental Analysis On Va Rof Modelmentioning

confidence: 99%

“…Therefore screening for such faults is important to reduce test escapes, infant mortality failures and reject rates. To optimize the screening and detection of resistive open faults (ROFs), testing methods employing multiple supply voltages have been investigated and proved to give good results [5], [6], [7], [8]. With the emergence of low power designs which utilize multiple supply voltage levels [9], multi-V DD -based methods are ow of critical concern for effective testing and diagnosis [10], [11], [12], [13], [14].…”

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confidence: 99%

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Multivoltage Aware Resistive Open Fault Model

Mohammadat

Ali

Hussin

et al. 2014

IEEE Trans. VLSI Syst.

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Abstract-Resistive open faults (ROFs) represent common interconnect manufacturing defects in VLSI designs and their behavior exhibits major dependencies on the supply voltage and test patterns. The widespread utilization of multiple supply voltages in contemporary VLSI designs poses a critical concern as to whether conventional models for resistive opens would still be effective. This is because conventional models do not explicitly model the VDD effect on fault behavior and detectability. Based on experimental analysis of ROFs in multi-VDD environment, we propose a voltage-aware model which divides the full range of open resistances (RO) into continuous behavioral intervals and three detectability ranges. The division of the behavior into intervals is based on monitoring the behavior change versus voltage across the resistance continuum, whereas the detectability ranges are based on finding minimum resistance for small and gross delay faults. It is highlighted that the detectable open resistance range is having a decreased trend with new technologies. Additionally it is shown that the observability of the unique increasing delay behavior with VDD for resistive open is reduced in new technologies. This poses reliability concerns and motivates the use of small delay testing for new technologies.

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“…Such variations can be beyond the performance variations caused by resistive smalldelay defects. Therefore, these process variations need to be detected to improve the reliability of chips [4]. Since they might escape detection during traditional Pass-Fail delay fault testing with functional clock, small-delay defects have become a significant problem and it is essential to detect such defects during manufacturing tests [5].…”

Section: Introductionmentioning

confidence: 99%

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion

Zhang

Namba

Ito

2014

IEICE Trans. Inf. & Syst.

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SUMMARYWith IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02∼47.74% with 6.33∼12.35% of hardware overhead.

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Distinguishing Resistive Small Delay Defects from Random Parameter Variations

Cited by 26 publications

References 21 publications

Screening small-delay defects using inter-path correlation to reduce reliability risk

Screening small-delay defects using inter-path correlation to reduce reliability risk

Multivoltage Aware Resistive Open Fault Model

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion

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