Distributed gate ESD network architecture for inter-power domain signals

ESD protection design for I/O libraries in advanced CMOS technologies

“…However, with internal core circuit failure it is more difficult to find out the ESD-induced failure site and fix the design. Since the internal core device failure is induced mainly by gate oxide damage, this makes it even more difficult to observe and quantify the ESD-induced failure [8,9].…”

ESD-induced internal core device failure: new failure modes in system-on-chip (SOC) designs

“…Otherwise signal lines act as an ESD discharge path from one power domain to another. However due to the increased chip size and [9][10] reported that CDM stress could cause the damage on internal receiver gate oxide due to excess voltage buildup in the signal lines.…”

“…However, with internal core circuit failure it is more difficult to pinpoint the ESD-induced failure site and fix the design. Since internal core device failure is induced mainly by gate oxide damage, this makes it even more difficult to observe and quantify the ESDinduced failure [8][9][10] The typical electrical failure signature after internal core circuit damage is: i) static I DD current increase in less than a 2 mA current range in general, ii) functional failure, and iii) scan chain breaks. This paper presents two major internal core device failure mechanisms observed in SOC designs using a 0.13-µm process technology.…”

Cumulative electrostatic discharge induced degradation of power-rail ESD clamp device in high-voltage CMOS/DMOS technologies

“…Bi-direction diode strings and other ESD clamp devices between two separated VDD (power) and two separated VSS (ground) nodes were proposed to overcome the internal ESD damage in a CMOS IC with multiple VDD/VSS pins by providing ESD current paths for all pin combinations of ESD test [1][2][3], as instructed in JEDEC standards for HBM and MM ESD sensitivity testing [4][5].…”