Distributed Pinning Spot Model for High-k Insulator - III-V Semiconductor Interfaces

Abstract

III-V metal-insulator-semiconductor (MIS) structures are recently attracting attentions as possible candidates of high-k gate stack for next generation CMOS transistors on the silicon platform. However, their basic electrical properties are not well understood. In order to further confirm the validity of the recently proposed distributed pinning-spot (DPS) model for anomalous admittance behavior of III-V MIS structures, we have carried out in this paper a detailed experimental and computer simulation study of a HfO2/GaAs high-k MIS structure controlled by a silicon interface control layer (Si ICL). It is clearly shown that the measured frequency dependences of C-V curves and admittance are far away from the predictions by the standard Si MOS theory. On the other hand, they can be well reproduced by the DPS model which assumes random spatial distribution of pinning spots with high densities of interface states in addition to pinning-free regions with low interface state densities. The model indicates that use of low-dimensional structures such as nanowires and nanodots may be beneficial for removal of pinning spots.

Charged Defect Quantification in Pt∕Al2O3∕In0.53Ga0.47As∕InP MOS Capacitors

“…1 and 4 or Eqs. 2 and 5, the difference of Q tot for the n-and p-type samples with the same oxide thickness and metal gate, is related directly to the interface state density [7] with 0.668 V representing the difference in the work function for p and n-type In 0.53 Ga 0.14 As doped to a similar level (4 Â 10 17 cm À3 ). Thus the difference in the V fb and Q tot values for n and p doped In 0.53 Ga 0.47 As can be used to separate the components of the fixed charge and the interface states.…”

“…[1][2][3][4][5] However, one major outstanding issue with these systems is the quantification of fixed charge at the dielectric-semiconductor interface, fixed charge in the bulk of the oxide, and interface states. 6 There has also been much discussion of the validity of analysis of the interface state density of these high mobility semiconductor systems using techniques such as the conductance method, 7 the high-low technique, 8 the Berglund method, 9 and the Terman method. 10 We have already reported on the nature of the fixed charge components in the atomic layer deposited (ALD)-Al 2 O 3 =n In 0.53 Ga 0.47 As system.…”

Reduction of interface state density at SiO2/InAlN interface by inserting ultrathin Al2O3 and plasma oxide interlayers

“…The residual frequency dispersion may have possibly resulted from the lateral nonuniform distribution of the interface states, which is still high near the conduction band ( E – E c > −0.2 eV). More specifically, there is a possibility that pinning spots distributed randomly where the Fermi level was pinned locally in a small (nm‐size) spot . Nevertheless, the average characteristics can be derived from the high‐frequency C – V curve.…”