DMA-Aware Memory Energy Management

Pandey, Vivek; Jiang, Weihang; Zhou, Yuanyuan; Bianchini, Ricardo

doi:10.1109/hpca.2006.1598120

Cited by 54 publications

(60 citation statements)

References 16 publications

(39 reference statements)

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“…Early works on reducing DRAM background power propose hardware and software policies for switching to low power DRAM modes [3][4][5][6], [18]. Our techniques further reduce DRAM background by servicing most of the required refreshes in the lowest power mode.…”

Section: Related Workmentioning

confidence: 99%

“…For example, in the deepest low power Self Refresh (SR) mode, the entire clocked DRAM circuitry is turned off, resulting in no additional power dissipation beyond the power required to refresh the DRAM cells. Many previous papers have proposed intelligent schemes to utilize these low power modes to save DRAM power [3][4][5][6][7][8]. The key idea behind these schemes is to switch a DRAM rank to a lower power mode whenever the rank stays idle for a time period longer than a pre-determined threshold.…”

Section: Introductionmentioning

confidence: 99%

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Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

Bhati

Chishti

Jacob

2013

International Symposium on Low Power Electronics and Design (ISLPED)

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Abstract-As the size and speed of DRAM devices increase, the performance and energy overheads due to refresh become more significant. To reduce refresh penalty we propose techniques referred collectively as "Coordinated Refresh", in which scheduling of low power modes and refresh commands are coordinated so that most of the required refreshes are issued when the DRAM device is in the deepest low power Self Refresh (SR) mode. Our approach saves DRAM background power because the peripheral circuitry and clocks are turned off in the SR mode. Our proposed solutions improve DRAM energy efficiency by 10% as compared to baseline, averaged across all the SPEC CPU 2006 benchmarks.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

Bhati

Chishti

Jacob

2013

International Symposium on Low Power Electronics and Design (ISLPED)

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“…As with processors, idle low-power states (e.g., precharge powerdown, self-refresh) have been extensively studied, e.g. [11,22,27,28,34]. However, past work has shown that active lowpower modes are more successful at garnering energy savings for server workloads [9,10,31].…”

Section: Memory Power Managementmentioning

confidence: 99%

“…Performance management. Similar to the approach initially proposed in [28] and later explored in [9,10,11,34], our policy is based on the notion of program slack: the difference between a baseline execution and a target latency penalty that a system operator is willing to incur on a program to save energy. The basic idea is that energy management often necessitates running the target program with reduced core or memory subsystem performance.…”

Section: Coscalementioning

confidence: 99%

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CoScale: Coordinating CPU and Memory System DVFS in Server Systems

Deng

Meisner

Bhattacharjee

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

179

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Recent work has introduced memory system dynamic voltage and frequency scaling (DVFS), and has suggested that balanced scaling of both CPU and the memory system is the most promising approach for conserving energy in server systems. In this paper, we first demonstrate that CPU and memory system DVFS often conflict when performed independently by separate controllers. In response, we propose CoScale, the first method for effectively coordinating these mechanisms under performance constraints. CoScale relies on execution profiling of each core via (existing and new) performance counters, and models of core and memory performance and power consumption. CoScale explores the set of possible frequency settings in such a way that it efficiently minimizes the full-system energy consumption within the performance bound. Our results demonstrate that, by effectively coordinating CPU and memory power management, CoScale conserves a significant amount of system energy compared to existing approaches, while consistently remaining within the prescribed performance bounds. The results also show that CoScale conserves almost as much system energy as an offline, idealized approach.

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A survey of the research on power management techniques for high‐performance systems

Liu

Zhu

2010

Softw Pract Exp

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This paper surveys the research on power management techniques for high performance systems. These include both commercial high performance clusters and scientific high performance computing (HPC) systems. Power consumption has rapidly risen to an intolerable scale. This results in both high operating costs and high failure rates so it is now a major cause for concern. It is imposed new challenges to the development of high performance systems. In this paper, we first review the basic mechanisms that underlie power management techniques. Then we survey two fundamental techniques for power management: metrics and profiling. After that, we review the research for the two major types of high performance systems: commercial clusters and supercomputers. Based on this, we discuss the new opportunities and problems presented by the recent adoption of virtualization techniques, and again we present the most recent research on this. Finally, we summarise and discuss future research directions.

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DMA-Aware Memory Energy Management

Abstract: Abstract

Cited by 54 publications

References 16 publications

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

CoScale: Coordinating CPU and Memory System DVFS in Server Systems

A survey of the research on power management techniques for high‐performance systems

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