DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs

Dhar, Ashutosh Sutra; Richter, Edward; Yu, Mang; Zuo, Wei; Wang, Xiaohao; Kim, Nam Sung; Chen, Deming

doi:10.1109/tc.2021.3137785

Cited by 9 publications

(2 citation statements)

References 12 publications

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“…Após o particionamento dos recursos no FPGA, existe ainda o desafio de definir qual tarefa será realizada em cada partição, ou seja, o posicionamento e escalonamento de tarefas dentro do dispositivo, como realizado em [Tang et al 2020, Yao et al 2022, Dhar et al 2022, porém para um único dispositivo. Em uma escala mais abrangente, esse problema ainda deve considerar que temos diversos nodos na infraestrutura, potencialmente com dispositivos de diferentes capacidades, dispostos com variadas distâncias do usuário final, e com diferentes cargas de ocupação.…”

Section: Arquiteturas Heterogêneas Em Infraestruturas Compartilhadasunclassified

Desafios para a Computação Energeticamente Eficiente

Carro,

Luca Nazar

2023

Escola De Computação PPGC/UFRGS 50 Anos: Transformando Desafios Em Oportunidades Para O Futuro

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New and relevant applications impose great challenges to computational systems, since they demand complex processing applied to large and growing amounts of data. With the weakening of Moore's law seen in recent years, new approaches are needed to deliver the required performance. An additional challenge is the need to contain the growing energy consumption of computing devices and infrastructures to reduce operating costs, for environmental reasons and, for mobile devices, also due to battery limitations. In this chapter, we will address the challenges of developing such systems and possible solutions, traversing the multiple levels of abstraction in computing. ResumoNovas e relevantes aplicações impõem grandes desafios a sistemas computacionais, já que demandam processamento complexo aplicado a grandes, e crescentes, quantidades de dados. Com a perda de força da lei de Moore observada nos últimos anos, novas abordagens são necessárias para oferecer o desempenho necessário. Soma-se a esse desafio a necessidade de contermos o crescente consumo energético de dispositivos e infraestruturas computacionais para redução de custos operacionais, por questões ambientais e, em dispositivos móveis, também por limitações de bateria. Nesse capítulo, iremos abordar os desafios de desenvolvimento de tais sistemas e possíveis soluções, atravessando os múltiplos níveis de abstração da computação.

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Section: Arquiteturas Heterogêneas Em Infraestruturas Compartilhadasunclassified

Desafios para a Computação Energeticamente Eficiente

Carro,

Luca Nazar

2023

Escola De Computação PPGC/UFRGS 50 Anos: Transformando Desafios Em Oportunidades Para O Futuro

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“…A plethora of existing work discussed the scheduling problem for general multi-core computing environments, which involve various software computing modules such as a CPU and a GPU [3], [4]. These algorithms take into account the different computation speeds of heterogeneous PEs as well as inter-core parallelism.…”

Section: Introductionmentioning

confidence: 99%

Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study

Ahmadi-Pour

Saha

Herdt

et al. 2022

2022 25th Euromicro Conference on Digital System Design (DSD)

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Heterogeneous platforms, that integrate CPU and FPGA-based processing units, are emerging as a promising solution for accelerating various applications in the embedded system domain. However, in this context, so far, comprehensive studies that combine theoretical features of real-time task scheduling with practical runtime architectural characteristics have mostly been ignored.To fill this gap, in this paper we propose a real-time scheduling algorithm with the objective of minimizing the overall execution time under hardware resource constraints for heterogeneous CPU+FPGA architectures. In particular, we propose an Integer Linear Programming (ILP) based technique for task allocation and scheduling. We then show how to implement a given scheduling on a practical CPU+FPGA system regarding current technology restrictions and validate our methodology using a practical RISC-V case-study. Our experiments demonstrate that performance gains of 40% and area usage reductions of 67% are possible compared to a full software and hardware execution, respectively.

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Hardware Implementation of Device Driver for an SPI Peripheral using High-Level Synthesis

Shinozaki,

Yamawaki

2024

2024 9th International Conference on Intelligent Informatics and Biomedical Sciences (ICIIBMS)

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DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs

Cited by 9 publications

References 12 publications

Desafios para a Computação Energeticamente Eficiente

Desafios para a Computação Energeticamente Eficiente

Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study

Hardware Implementation of Device Driver for an SPI Peripheral using High-Level Synthesis

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